events

跨平台性能调试工具

#Group 43 pm_branch1, Branch operations
event:0X02B0 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP43 : (Group 43 pm_branch1) Unconditional branch
event:0X02B1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, target prediction
event:0X02B2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, CR prediction
event:0X02B3 counters:3 um:zero minimum:1000 name:PM_BR_PRED_CR_TA_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, CR and target prediction

#Group 44 pm_branch2, Branch operations
event:0X02C0 counters:0 um:zero minimum:1000 name:PM_GRP_BR_REDIR_NONSPEC_GRP44 : (Group 44 pm_branch2) Group experienced non-speculative branch redirect
event:0X02C1 counters:1 um:zero minimum:1000 name:PM_GRP_BR_REDIR_GRP44 : (Group 44 pm_branch2) Group experienced branch redirect
event:0X02C2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP44 : (Group 44 pm_branch2) Flush caused by branch mispredict
event:0X02C3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP44 : (Group 44 pm_branch2) Internal operations completed

#Group 45 pm_L1_tlbmiss, L1 load and TLB misses
event:0X02D0 counters:0 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP45 : (Group 45 pm_L1_tlbmiss) Cycles doing data tablewalks
event:0X02D1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP45 : (Group 45 pm_L1_tlbmiss) Data TLB misses
event:0X02D2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load misses
event:0X02D3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load references

#Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
event:0X02E0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP46 : (Group 46 pm_L1_DERAT_miss) Data loaded from L2
event:0X02E1 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP46 : (Group 46 pm_L1_DERAT_miss) DERAT misses
event:0X02E2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP46 : (Group 46 pm_L1_DERAT_miss) L1 D cache store references
event:0X02E3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP46 : (Group 46 pm_L1_DERAT_miss) L1 D cache store misses

#Group 47 pm_L1_slbmiss, L1 load and SLB misses
event:0X02F0 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP47 : (Group 47 pm_L1_slbmiss) Data SLB misses
event:0X02F1 counters:1 um:zero minimum:1000 name:PM_ISLB_MISS_GRP47 : (Group 47 pm_L1_slbmiss) Instruction SLB misses
event:0X02F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP47 : (Group 47 pm_L1_slbmiss) LSU0 L1 D cache load misses
event:0X02F3 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP47 : (Group 47 pm_L1_slbmiss) LSU1 L1 D cache load misses

#Group 48 pm_dtlbref, Data TLB references
event:0X0300 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_4K_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 4K page
event:0X0301 counters:1 um:zero minimum:1000 name:PM_DTLB_REF_64K_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 64K page
event:0X0302 counters:2 um:zero minimum:1000 name:PM_DTLB_REF_16M_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 16M page
event:0X0303 counters:3 um:zero minimum:1000 name:PM_DTLB_REF_16G_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 16G page

#Group 49 pm_dtlbmiss, Data TLB misses
event:0X0310 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_4K_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 4K page
event:0X0311 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_64K_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 64K page
event:0X0312 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_16M_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 16M page
event:0X0313 counters:3 um:zero minimum:1000 name:PM_DTLB_MISS_16G_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 16G page

#Group 50 pm_dtlb, Data TLB references and misses
event:0X0320 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_GRP50 : (Group 50 pm_dtlb) Data TLB references
event:0X0321 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP50 : (Group 50 pm_dtlb) Data TLB misses
event:0X0322 counters:2 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_dtlb) Processor cycles
event:0X0323 counters:3 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_dtlb) Processor cycles

#Group 51 pm_L1_refmiss, L1 load references and misses and store references and misses
event:0X0330 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache load references
event:0X0331 counters:1 um:zero minimum:1000 name:PM_ST_REF_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache store references
event:0X0332 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache load misses
event:0X0333 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache store misses

#Group 52 pm_dsource1, L3 cache and memory data access
event:0X0340 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP52 : (Group 52 pm_dsource1) Data loaded from L3
event:0X0341 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP52 : (Group 52 pm_dsource1) Data loaded from local memory
event:0X0342 counters:2 um:zero minimum:1000 name:PM_FLUSH_GRP52 : (Group 52 pm_dsource1) Flushes
event:0X0343 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP52 : (Group 52 pm_dsource1) Internal operations completed

#Group 53 pm_dsource2, L3 cache and memory data access
event:0X0350 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP53 : (Group 53 pm_dsource2) Data loaded from L3
event:0X0351 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP53 : (Group 53 pm_dsource2) Data loaded from local memory
event:0X0352 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP53 : (Group 53 pm_dsource2) Data loaded missed L2
event:0X0353 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP53 : (Group 53 pm_dsource2) Data loaded from remote memory

#Group 54 pm_dsource_L2, L2 cache data access
event:0X0360 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.5 shared
event:0X0361 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.5 modified
event:0X0362 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.75 shared
event:0X0363 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.75 modified

#Group 55 pm_dsource_L3, L3 cache data access
event:0X0370 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.5 shared
event:0X0371 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.5 modified
event:0X0372 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L375_SHR_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.75 shared
event:0X0373 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L375_MOD_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.75 modified

#Group 56 pm_isource1, Instruction source information
event:0X0380 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP56 : (Group 56 pm_isource1) Instruction fetched from L3
event:0X0381 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP56 : (Group 56 pm_isource1) Instruction fetched from L1
event:0X0382 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP56 : (Group 56 pm_isource1) Instruction fetched from prefetch
event:0X0383 counters:3 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP56 : (Group 56 pm_isource1) Instruction fetched from remote memory

#Group 57 pm_isource2, Instruction source information
event:0X0390 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP57 : (Group 57 pm_isource2) Instruction fetched from L2
event:0X0391 counters:1 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP57 : (Group 57 pm_isource2) Instruction fetched from local memory
event:0X0392 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP57 : (Group 57 pm_isource2) Internal operations completed
event:0X0393 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP57 : (Group 57 pm_isource2) No instructions fetched

#Group 58 pm_isource_L2, L2 instruction source information
event:0X03A0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L25_SHR_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.5 shared
event:0X03A1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.5 modified
event:0X03A2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L275_SHR_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.75 shared
event:0X03A3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L275_MOD_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.75 modified

#Group 59 pm_isource_L3, L3 instruction source information
event:0X03B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L35_SHR_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.5 shared
event:0X03B1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L35_MOD_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.5 modified
event:0X03B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L375_SHR_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.75 shared
event:0X03B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L375_MOD_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.75 modified

#Group 60 pm_pteg_source1, PTEG source information
event:0X03C0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L25_SHR_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.5 shared
event:0X03C1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L25_MOD_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.5 modified
event:0X03C2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L275_SHR_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.75 shared
event:0X03C3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L275_MOD_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.75 modified

#Group 61 pm_pteg_source2, PTEG source information
event:0X03D0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L35_SHR_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.5 shared
event:0X03D1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L35_MOD_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.5 modified
event:0X03D2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L375_SHR_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.75 shared
event:0X03D3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L375_MOD_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.75 modified

#Group 62 pm_pteg_source3, PTEG source information
event:0X03E0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from L2
event:0X03E1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from local memory
event:0X03E2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from L2 miss
event:0X03E3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from remote memory

#Group 63 pm_pteg_source4, L3 PTEG and group disptach events
event:0X03F0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP63 : (Group 63 pm_pteg_source4) PTEG loaded from L3
event:0X03F1 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_GRP63 : (Group 63 pm_pteg_source4) Group dispatches
event:0X03F2 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_SUCCESS_GRP63 : (Group 63 pm_pteg_source4) Group dispatch success
event:0X03F3 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP63 : (Group 63 pm_pteg_source4) L1 D cache entries invalidated from L2

#Group 64 pm_L2SA_ld, L2 slice A load events
event:0X0400 counters:0 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt
event:0X0401 counters:1 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt failed due to all RC full
event:0X0402 counters:2 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
event:0X0403 counters:3 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt failed due to other reasons

#Group 65 pm_L2SA_st, L2 slice A store events
event:0X0410 counters:0 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt
event:0X0411 counters:1 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt failed due to all RC full
event:0X0412 counters:2 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_ADDR_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
event:0X0413 counters:3 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_OTHER_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt failed due to other reasons