events

跨平台性能调试工具

#Group 20 pm_lsu_reject5, LSU misc reject and flush events
event:0X0140 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_SRQ_GRP20 : (Group 20 pm_lsu_reject5) LSU SRQ lhs rejects
event:0X0141 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_RELOAD_CDF_GRP20 : (Group 20 pm_lsu_reject5) LSU reject due to reload CDF or tag update collision
event:0X0142 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP20 : (Group 20 pm_lsu_reject5) Flush initiated by LSU
event:0X0143 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP20 : (Group 20 pm_lsu_reject5) Flushes

#Group 21 pm_flush1, Misc flush events
event:0X0150 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP21 : (Group 21 pm_flush1) Internal operations completed
event:0X0151 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP21 : (Group 21 pm_flush1) SRQ unaligned store flushes
event:0X0152 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP21 : (Group 21 pm_flush1) Flush caused by thread GCT imbalance
event:0X0153 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP21 : (Group 21 pm_flush1) L1 D cache entries invalidated from L2

#Group 22 pm_flush2, Flushes due to scoreboard and sync
event:0X0160 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
event:0X0161 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP22 : (Group 22 pm_flush2) Internal operations completed
event:0X0162 counters:2 um:zero minimum:1000 name:PM_FLUSH_SB_GRP22 : (Group 22 pm_flush2) Flush caused by scoreboard operation
event:0X0163 counters:3 um:zero minimum:1000 name:PM_FLUSH_SYNC_GRP22 : (Group 22 pm_flush2) Flush caused by sync

#Group 23 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
event:0X0170 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) SRQ flushes
event:0X0171 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) LRQ flushes
event:0X0172 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Internal operations completed
event:0X0173 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Flush initiated by LSU

#Group 24 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
event:0X0180 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP24 : (Group 24 pm_lsu_flush_lrq) LSU0 LRQ flushes
event:0X0181 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP24 : (Group 24 pm_lsu_flush_lrq) LSU1 LRQ flushes
event:0X0182 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP24 : (Group 24 pm_lsu_flush_lrq) Flush initiated by LSU
event:0X0183 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP24 : (Group 24 pm_lsu_flush_lrq) Internal operations completed

#Group 25 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
event:0X0190 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP25 : (Group 25 pm_lsu_flush_srq) LSU0 SRQ lhs flushes
event:0X0191 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP25 : (Group 25 pm_lsu_flush_srq) LSU1 SRQ lhs flushes
event:0X0192 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP25 : (Group 25 pm_lsu_flush_srq) Internal operations completed
event:0X0193 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP25 : (Group 25 pm_lsu_flush_srq) Flush initiated by LSU

#Group 26 pm_lsu_flush_unaligned, LSU flush due to unaligned data
event:0X01A0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP26 : (Group 26 pm_lsu_flush_unaligned) LRQ unaligned load flushes
event:0X01A1 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP26 : (Group 26 pm_lsu_flush_unaligned) SRQ unaligned store flushes
event:0X01A2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_lsu_flush_unaligned) Branches issued
event:0X01A3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP26 : (Group 26 pm_lsu_flush_unaligned) Internal operations completed

#Group 27 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
event:0X01B0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP27 : (Group 27 pm_lsu_flush_uld) LSU0 unaligned load flushes
event:0X01B1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP27 : (Group 27 pm_lsu_flush_uld) LSU1 unaligned load flushes
event:0X01B2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP27 : (Group 27 pm_lsu_flush_uld) Flush initiated by LSU
event:0X01B3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP27 : (Group 27 pm_lsu_flush_uld) Internal operations completed

#Group 28 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
event:0X01C0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP28 : (Group 28 pm_lsu_flush_ust) LSU0 unaligned store flushes
event:0X01C1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP28 : (Group 28 pm_lsu_flush_ust) LSU1 unaligned store flushes
event:0X01C2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP28 : (Group 28 pm_lsu_flush_ust) Internal operations completed
event:0X01C3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP28 : (Group 28 pm_lsu_flush_ust) Flush initiated by LSU

#Group 29 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
event:0X01D0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_FULL_GRP29 : (Group 29 pm_lsu_flush_full) Flush caused by LRQ full
event:0X01D1 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP29 : (Group 29 pm_lsu_flush_full) Internal operations completed
event:0X01D2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP29 : (Group 29 pm_lsu_flush_full) Marked LRQ flushes
event:0X01D3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_FULL_GRP29 : (Group 29 pm_lsu_flush_full) Flush caused by SRQ full

#Group 30 pm_lsu_stall1, LSU Stalls
event:0X01E0 counters:0 um:zero minimum:1000 name:PM_GRP_MRK_GRP30 : (Group 30 pm_lsu_stall1) Group marked in IDU
event:0X01E1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by LSU instruction
event:0X01E2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP30 : (Group 30 pm_lsu_stall1) Internal operations completed
event:0X01E3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by reject

#Group 31 pm_lsu_stall2, LSU Stalls
event:0X01F0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP31 : (Group 31 pm_lsu_stall2) Internal operations completed
event:0X01F1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP31 : (Group 31 pm_lsu_stall2) Completion stall caused by D cache miss
event:0X01F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_lsu_stall2) Processor cycles
event:0X01F3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP31 : (Group 31 pm_lsu_stall2) Completion stall caused by ERAT miss

#Group 32 pm_fxu_stall, FXU Stalls
event:0X0200 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP32 : (Group 32 pm_fxu_stall) Group experienced non-speculative I cache miss or branch redirect
event:0X0201 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by FXU instruction
event:0X0202 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP32 : (Group 32 pm_fxu_stall) Internal operations completed
event:0X0203 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by DIV instruction

#Group 33 pm_fpu_stall, FPU Stalls
event:0X0210 counters:0 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP33 : (Group 33 pm_fpu_stall) Cycles FPU issue queue full
event:0X0211 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP33 : (Group 33 pm_fpu_stall) Completion stall caused by FDIV or FQRT instruction
event:0X0212 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP33 : (Group 33 pm_fpu_stall) Internal operations completed
event:0X0213 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP33 : (Group 33 pm_fpu_stall) Completion stall caused by FPU instruction

#Group 34 pm_queue_full, BRQ LRQ LMQ queue full
event:0X0220 counters:0 um:zero minimum:1000 name:PM_LARX_LSU0_GRP34 : (Group 34 pm_queue_full) Larx executed on LSU0
event:0X0221 counters:1 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles branch queue full
event:0X0222 counters:2 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles LRQ full
event:0X0223 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles LMQ full

#Group 35 pm_issueq_full, FPU FX full
event:0X0230 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FPU0 issue queue full
event:0X0231 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FPU1 issue queue full
event:0X0232 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FXU0/LS0 queue full
event:0X0233 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FXU1/LS1 queue full

#Group 36 pm_mapper_full1, CR CTR GPR mapper full
event:0X0240 counters:0 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles CR logical operation mapper full
event:0X0241 counters:1 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles LR/CTR mapper full
event:0X0242 counters:2 um:zero minimum:1000 name:PM_GPR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles GPR mapper full
event:0X0243 counters:3 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles CR issue queue full

#Group 37 pm_mapper_full2, FPR XER mapper full
event:0X0250 counters:0 um:zero minimum:1000 name:PM_FPR_MAP_FULL_CYC_GRP37 : (Group 37 pm_mapper_full2) Cycles FPR mapper full
event:0X0251 counters:1 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP37 : (Group 37 pm_mapper_full2) Cycles XER mapper full
event:0X0252 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP37 : (Group 37 pm_mapper_full2) Marked data loaded missed L2
event:0X0253 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP37 : (Group 37 pm_mapper_full2) Internal operations completed

#Group 38 pm_misc_load, Non-cachable loads and stcx events
event:0X0260 counters:0 um:zero minimum:1000 name:PM_STCX_FAIL_GRP38 : (Group 38 pm_misc_load) STCX failed
event:0X0261 counters:1 um:zero minimum:1000 name:PM_STCX_PASS_GRP38 : (Group 38 pm_misc_load) Stcx passes
event:0X0262 counters:2 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP38 : (Group 38 pm_misc_load) LSU0 non-cacheable loads
event:0X0263 counters:3 um:zero minimum:1000 name:PM_LSU1_NCLD_GRP38 : (Group 38 pm_misc_load) LSU1 non-cacheable loads

#Group 39 pm_ic_demand, ICache demand from BR redirect
event:0X0270 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_REJECT_GRP39 : (Group 39 pm_ic_demand) LSU0 busy due to reject
event:0X0271 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_REJECT_GRP39 : (Group 39 pm_ic_demand) LSU1 busy due to reject
event:0X0272 counters:2 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP39 : (Group 39 pm_ic_demand) L2 I cache demand request due to BHT redirect
event:0X0273 counters:3 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP39 : (Group 39 pm_ic_demand) L2 I cache demand request due to branch redirect

#Group 40 pm_ic_pref, ICache prefetch
event:0X0280 counters:0 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP40 : (Group 40 pm_ic_pref) Translation written to ierat
event:0X0281 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP40 : (Group 40 pm_ic_pref) Instruction prefetch requests
event:0X0282 counters:2 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP40 : (Group 40 pm_ic_pref) Instruction prefetched installed in prefetch buffer
event:0X0283 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP40 : (Group 40 pm_ic_pref) No instructions fetched

#Group 41 pm_ic_miss, ICache misses
event:0X0290 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_NONSPEC_GRP41 : (Group 41 pm_ic_miss) Group experienced non-speculative I cache miss
event:0X0291 counters:1 um:zero minimum:1000 name:PM_GRP_IC_MISS_GRP41 : (Group 41 pm_ic_miss) Group experienced I cache miss
event:0X0292 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP41 : (Group 41 pm_ic_miss) L1 reload data source valid
event:0X0293 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP41 : (Group 41 pm_ic_miss) Internal operations completed

#Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
event:0X02A0 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP42 : (Group 42 pm_branch_miss) TLB misses
event:0X02A1 counters:1 um:zero minimum:1000 name:PM_SLB_MISS_GRP42 : (Group 42 pm_branch_miss) SLB misses
event:0X02A2 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP42 : (Group 42 pm_branch_miss) Branch mispredictions due to CR bit setting
event:0X02A3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP42 : (Group 42 pm_branch_miss) Branch mispredictions due to target address