events

跨平台性能调试工具

#ppc64 Cell Broadband Engine events
#
# Copyright OProfile authors
#
#(C) COPYRIGHT International Business Machines Corp. 2006
# Contributed by Maynard Johnson <[e-mail]>
#
#
#  As many as 4 signals may be specified when they are from the same group.
#  In some instances, signals from other groups in the same island or one
#  other island may also be specified.
#
#  Each signal is assigned to a unique counter.  There are 4 32-bit hardware
#  counters.  The signals are defined in the Cell Broadband Engine
#  Performance manual.
#
#  Each event is given a unique event number.  The event number is used by the
#  Oprofile code to resolve event names for the postprocessing.  This is done
#  to preserve compatibility with the rest of the Oprofile code.  The event
#  number format group_num followed by the counter number for the event within
#  the group.

# Signal Default
event:0x1 counters:0,1,2,3 um:zero minimum:100000 name:CYCLES : Processor Cycles
event:0x2 counters:0,1,2,3 um:zero minimum:60000 name:SPU_CYCLES : SPU Processor Cycles


# Cell BE Island 2 - PowerPC Processing Unit (PPU)

# CBE Signal Group 21 - PPU Instruction Unit - Group 1 (NClk)
event:0x834 counters:0,1,2,3 um:PPU_01_edges           minimum:10000 	name:Branch_Commit		: Branch instruction committed. 
event:0x835 counters:0,1,2,3 um:PPU_01_edges           minimum:10000	name:Branch_Flush		: Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1]. 
event:0x836 counters:0,1,2,3 um:PPU_01_cycles          minimum:10000	name:Ibuf_Empty		: Instruction buffer empty. 
event:0x837 counters:0,1,2,3 um:PPU_01_edges           minimum:10000	name:IERAT_Miss		: Instruction effective-address-to-real-address translation (I-ERAT) miss. 
event:0x838 counters:0,1,2,3 um:PPU_01_cycles_or_edges minimum:10000	name:IL1_Miss_Cycles	: L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1). 
event:0x83a counters:0,1,2,3 um:PPU_01_cycles          minimum:10000	name:Dispatch_Blocked	: Valid instruction available for dispatch, but dispatch is blocked.
event:0x83d counters:0,1,2,3 um:PPU_01_edges           minimum:10000	name:Instr_Flushed		: Instruction in pipeline stage EX7 causes a flush. 
event:0x83f counters:0,1,2,3 um:PPU_01_edges           minimum:10000	name:PPC_Commit		: Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle. 


# CBE Signal Group 22 - PPU Execution Unit (NClk)
event:0x89a counters:0,1,2,3 um:PPU_01_cycles          minimum:10000	name:DERAT_Miss		: Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative. 
event:0x89b counters:0,1,2,3 um:PPU_01_cycles          minimum:10000	name:Store_Request		: Store request counted at the L2 interface. Counts microcoded PPE sequences more than once (see Note 1 for exceptions). (Thread 0 and 1)
event:0x89c counters:0,1,2,3 um:PPU_01_cycles          minimum:10000	name:Load_Valid		: Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions. 
event:0x89d counters:0,1,2,3 um:PPU_01_cycles          minimum:10000	name:DL1_Miss		: L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well. 


# Cell BE Island 3 - PowerPC Storage Subsystem (PPSS)

# CBE Signal Group 31 - PPSS Bus Interface Unit (NClk/2)
event:0xc1c counters:0,1,2,3 um:PPU_2_edges           minimum:10000	name:rcv_mmio_rd_ev	: Load from MFC memory-mapped I/O (MMIO) space.
event:0xc1d counters:0,1,2,3 um:PPU_2_edges           minimum:10000	name:rcv_mmio_wr_ev	: Stores to MFC MMIO space.
event:0xc22 counters:0,1,2,3 um:PPU_2_edges           minimum:10000	name:even_token_req_ev	: Request token for even memory bank numbers 0-14.
event:0xc2b counters:0,1,2,3 um:PPU_2_edges           minimum:10000	name:rcv_data_ev		: Receive 8-beat data from the Element Interconnect Bus (EIB).
event:0xc2c counters:0,1,2,3 um:PPU_2_edges           minimum:10000	name:send_data_ev		: Send 8-beat data to the EIB.
event:0xc2d counters:0,1,2,3 um:PPU_2_edges           minimum:10000	name:send_cmd_ev		: Send a command to the EIB; includes retried commands.
event:0xc2e counters:0,1,2,3 um:PPU_2_cycles          minimum:10000	name:dgnt_dly_cy		: Cycles between data request and data grant.
event:0xc33 counters:0,1,2,3 um:PPU_2_cycles          minimum:10000	name:nc_wr_not_emp_cy	: The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty.


# CBE Signal Group 32 - PPSS L2 Cache Controller - Group 1 (NClk/2)
event:0xc80 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:cache_hit		: Cache hit for core interface unit (CIU) loads and stores.
event:0xc81 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:cache_miss		: Cache miss for CIU loads and stores.
event:0xc84 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:load_miss		: CIU load miss.
event:0xc85 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:store_miss		: CIU store to Invalid state (miss).
event:0xc87 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:larx_miss_th1		: Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state
event:0xc8e counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:stcx_miss_th1		: Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set.
event:0xc99 counters:0,1,2,3 um:PPU_02_cycles          minimum:10000	name:all_snp_busy		: All four snoop state machines busy.

# CBE Signal Group 33 - PPSS L2 Cache Controller - Group 2 (NClk/2)
event:0xce8 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:dclaim_srt		: Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state (see Note 1).
event:0xcef counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:dclaim_to_rwitm	: Dclaim converted into rwitm; may still not get to the bus if stcx is aborted (see Note 2).
event:0xcf0 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:store_mxe		: Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state.
event:0xcf1 counters:0,1,2,3 um:PPU_02_cycles          minimum:10000	name:stq_full		: 8-entry store queue (STQ) full.
event:0xcf2 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:store_rc_ack		: Store dispatched to RC machine is acknowledged.
event:0xcf3 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:gather_store		: Gatherable store (type = 00000) received from CIU.
event:0xcf6 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_push		: Snoop push.
event:0xcf7 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:intv_snode_er		: Send intervention from (SL | E) cache state to a destination within the same CBE chip.
event:0xcf8 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:intv_snode_mx		: Send intervention from (M | MU) cache state to a destination within the same CBE chip.
event:0xcfd counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_retry		: Respond with Retry to a snooped request due to one of the following conflicts: read-and-claim state machine (RC) full address, castout (CO) congruence class, snoop (SNP) machine full address, all snoop machines busy, directory lockout, or parity error.
event:0xcfe counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_busy_retry	: Respond with Retry to a snooped request because all snoop machines are busy.
event:0xcff counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_mx_to_est		: Snooped response causes a cache state transition from (M | MU) to (E | S | T).
event:0xd00 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_e_to_s		: Snooped response causes a cache state transition from E to S.
event:0xd01 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_esrt_to_i		: Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I).
event:0xd02 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:snp_mx_to_i		: Snooped response causes a cache state transition from (M | MU) to I.

# CBE Signal Group 34 - PPSS L2 Cache Controller - Group 3 (NClk/2)
event:0xd54 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:larx_miss		: Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state.
event:0xd5b counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:stcx_miss_th2		: Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state.

# CBE Signal Group 35 - PPSS Non-Cacheable Unit (NClk/2)
event:0xdac counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:st_req_any		: Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio.
event:0xdad counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:st_req_sync		: sync received from CIU.
event:0xdb0 counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:st_req_store		: Non-cacheable store request received from CIU; includes only stores.
event:0xdb2 counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:st_req_eieio		: eieio received from CIU.
event:0xdb3 counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:st_req_tlbie		: tlbie received from CIU.
event:0xdb4 counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stq_bot_sync		: sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2.
event:0xdb5 counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stq_bot_lsync		: lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2.
event:0xdb6 counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stq_bot_eieio		: eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2.
event:0xdb7 counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stq_bot_tlbieg	: tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU.
event:0xdb8 counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:st_combined		: Non-cacheable store combined with the previous non-cacheable store with a contiguous address.
event:0xdb9 counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:ld_cancel		: Load request canceled by CIU due to late detection of load-hit-store condition (128B boundary).
event:0xdba counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:ld_hit_st		: NCU detects a load hitting a previous store to an overlapping address (32B boundary).
event:0xdbb counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stb_full		: All four store-gather buffers full.
event:0xdbc counters:0,1,2,3 um:PPU_0_edges           minimum:10000	name:ld_req		: Non-cacheable load request received from CIU; includes instruction and data fetches.
event:0xdbd counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stq_not_empty		: The four-deep store queue not empty.
event:0xdbe counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stq_full		: The four-deep store queue full.
event:0xdbf counters:0,1,2,3 um:PPU_0_cycles          minimum:10000	name:stb_not_empty		: At least one store gather buffer not empty.

# Cell BE Island 4 - Synergistic Processor Unit (SPU)

# CBE Signal Group 41 - SPU (NClk)

# CBE Signal Group 42 - SPU Trigger (NClk)

# CBE Signal Group 43 - SPU Event (NClk)

# Cell BE Island 6 - Element Interconnect Bus (EIB)

# CBE Signal Group 61 - EIB Address Concentrator 0 (NClk/2)
event:0x17d4 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:WAC0_W_ICMD_PERF(0)	: Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 1)
event:0x17d5 counters:0,1,2,3 um:PPU_02_edges           minimum:10000	name:WAC0_W_ICMD_PERF(1)	: Number of dclaim commands (including atomic) AC1 to AC0. (Group 1)