📄 mcf5272.h
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Mcf5272_iord(IMMP,MCF5272_QSPI_QDLYR,16)
#define MCF5272_RD_QSPI_QWR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_QSPI_QWR,16)
#define MCF5272_RD_QSPI_QIR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_QSPI_QIR,16)
#define MCF5272_RD_QSPI_QAR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_QSPI_QAR,16)
#define MCF5272_RD_QSPI_QDR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_QSPI_QDR,16)
/* Write access macros for general use */
#define MCF5272_WR_QSPI_QMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_QSPI_QMR,16,DATA)
#define MCF5272_WR_QSPI_QDLYR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_QSPI_QDLYR,16,DATA)
#define MCF5272_WR_QSPI_QWR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_QSPI_QWR,16,DATA)
#define MCF5272_WR_QSPI_QIR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_QSPI_QIR,16,DATA)
#define MCF5272_WR_QSPI_QAR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_QSPI_QAR,16,DATA)
#define MCF5272_WR_QSPI_QDR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_QSPI_QDR,16,DATA)
/**********************************************************************
*
* PWM Module Registers Description
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5272_PWM_PWMCR1 (0x00C0)
#define MCF5272_PWM_PWMCR2 (0x00C4)
#define MCF5272_PWM_PWMCR3 (0x00C8)
#define MCF5272_PWM_PWMWD1 (0x00D0)
#define MCF5272_PWM_PWMWD2 (0x00D4)
#define MCF5272_PWM_PWMWD3 (0x00D8)
/* Read access macros for general use */
#define MCF5272_RD_PWM_PWMCR1(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR1,8)
#define MCF5272_RD_PWM_PWMCR2(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR2,8)
#define MCF5272_RD_PWM_PWMCR3(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR3,8)
#define MCF5272_RD_PWM_PWMWD1(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD1,8)
#define MCF5272_RD_PWM_PWMWD2(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD2,8)
#define MCF5272_RD_PWM_PWMWD3(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD3,8)
/* Write access macros for general use */
#define MCF5272_WR_PWM_PWMCR1(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR1,8,DATA)
#define MCF5272_WR_PWM_PWMCR2(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR2,8,DATA)
#define MCF5272_WR_PWM_PWMCR3(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR3,8,DATA)
#define MCF5272_WR_PWM_PWMWD1(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD1,8,DATA)
#define MCF5272_WR_PWM_PWMWD2(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD2,8,DATA)
#define MCF5272_WR_PWM_PWMWD3(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD3,8,DATA)
/**********************************************************************
*
* DMA Module Registers Description
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5272_DMA_DCMR (0x00E0)
#define MCF5272_DMA_DCIR (0x00E6)
#define MCF5272_DMA_DBCR (0x00E8)
#define MCF5272_DMA_DSAR (0x00EC)
#define MCF5272_DMA_DDAR (0x00F0)
/* Read access macros for general use */
#define MCF5272_RD_DMA_DCMR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DCMR,32)
#define MCF5272_RD_DMA_DCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DCIR,16)
#define MCF5272_RD_DMA_DBCR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DBCR,32)
#define MCF5272_RD_DMA_DSAR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DSAR,32)
#define MCF5272_RD_DMA_DDAR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DDAR,32)
/* Write access macros for general use */
#define MCF5272_WR_DMA_DCMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_DMA_DCMR,32,DATA)
#define MCF5272_WR_DMA_DCIR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_DMA_DCIR,16,DATA)
#define MCF5272_WR_DMA_DBCR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_DMA_DBCR,32,DATA)
#define MCF5272_WR_DMA_DSAR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_DMA_DSAR,32,DATA)
#define MCF5272_WR_DMA_DDAR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_DMA_DDAR,32,DATA)
/* Bit level definitions and macros */
#define MCF5272_DMA_DCMR_RESET (0x80000000)
#define MCF5272_DMA_DCMR_EN (0x40000000)
#define MCF5272_DMA_DCMR_RQM (0x000C0000)
#define MCF5272_DMA_DCMR_DSTM_INC (0x00002000)
#define MCF5272_DMA_DCMR_DSTT_UD (0x00000400)
#define MCF5272_DMA_DCMR_DSTT_UC (0x00000800)
#define MCF5272_DMA_DCMR_DSTT_SD (0x00001400)
#define MCF5272_DMA_DCMR_DSTT_SC (0x00001800)
#define MCF5272_DMA_DCMR_DSTS_LW (0x00000000)
#define MCF5272_DMA_DCMR_DSTS_B (0x00000100)
#define MCF5272_DMA_DCMR_DSTS_W (0x00000200)
#define MCF5272_DMA_DCMR_DSTS_LINE (0x00000300)
#define MCF5272_DMA_DCMR_SRCM_INC (0x00000020)
#define MCF5272_DMA_DCMR_SRCT_UD (0x00000004)
#define MCF5272_DMA_DCMR_SRCT_UC (0x00000008)
#define MCF5272_DMA_DCMR_SRCT_SD (0x00000014)
#define MCF5272_DMA_DCMR_SRCT_SC (0x00000018)
#define MCF5272_DMA_DCMR_SRCS_LW (0x00000000)
#define MCF5272_DMA_DCMR_SRCS_B (0x00000001)
#define MCF5272_DMA_DCMR_SRCS_W (0x00000002)
#define MCF5272_DMA_DCMR_SRCS_LINE (0x00000003)
#define MCF5272_DMA_DCIR_INVEN (0x1000)
#define MCF5272_DMA_DCIR_ASCEN (0x0800)
#define MCF5272_DMA_DCIR_TEEN (0x0200)
#define MCF5272_DMA_DCIR_TCEN (0x0100)
#define MCF5272_DMA_DCIR_INV (0x0010)
#define MCF5272_DMA_DCIR_ASC (0x0008)
#define MCF5272_DMA_DCIR_TE (0x0002)
#define MCF5272_DMA_DCIR_TC (0x0001)
/**********************************************************************
*
* USART Module Registers Description
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5272_UART0_UMR (0x0100) /* RW */
#define MCF5272_UART0_USR (0x0104) /* USR RO, UCSR WO */
#define MCF5272_UART0_UCR (0x0108) /* WO */
#define MCF5272_UART0_UBUF (0x010C) /* URB RO, UTB WO */
#define MCF5272_UART0_UCCR (0x0110) /* UCCR RO, UACR WO */
#define MCF5272_UART0_UISR (0x0114) /* UISR RO, UIMR WO */
#define MCF5272_UART0_UBG1 (0x0118) /* WO */
#define MCF5272_UART0_UBG2 (0x011C) /* WO */
#define MCF5272_UART0_UABR1 (0x0120) /* RO */
#define MCF5272_UART0_UABR2 (0x0124) /* RO */
#define MCF5272_UART0_UTFCSR (0x0128) /* RW */
#define MCF5272_UART0_URFCSR (0x012C) /* RW */
#define MCF5272_UART0_UIP (0x0134) /* RO */
#define MCF5272_UART0_UOP1 (0x0138) /* WO */
#define MCF5272_UART0_UOP0 (0x013C) /* WO */
#define MCF5272_UART1_UMR (0x0140) /* RW */
#define MCF5272_UART1_USR (0x0144) /* USR RO, UCSR WO */
#define MCF5272_UART1_UCR (0x0148) /* WO */
#define MCF5272_UART1_UBUF (0x014C) /* URB RO, UTB WO */
#define MCF5272_UART1_UCCR (0x0150) /* UCCR RO, UACR WO */
#define MCF5272_UART1_UISR (0x0154) /* UISR RO, UIMR WO */
#define MCF5272_UART1_UBG1 (0x0158) /* WO */
#define MCF5272_UART1_UBG2 (0x015C) /* WO */
#define MCF5272_UART1_UABR1 (0x0160) /* RO */
#define MCF5272_UART1_UABR2 (0x0164) /* RO */
#define MCF5272_UART1_UTFCSR (0x0168) /* RW */
#define MCF5272_UART1_URFCSR (0x016C) /* RW */
#define MCF5272_UART1_UIP (0x0174) /* RO */
#define MCF5272_UART1_UOP1 (0x0178) /* WO */
#define MCF5272_UART1_UOP0 (0x017C) /* WO */
/* Read access macros for general use */
#define MCF5272_RD_UART0_UMR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UMR,8)
#define MCF5272_RD_UART0_USR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_USR,8)
#define MCF5272_RD_UART0_URB(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UBUF,8)
#define MCF5272_RD_UART0_UCCR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UCCR,8)
#define MCF5272_RD_UART0_UISR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UISR,8)
#define MCF5272_RD_UART0_UABR1(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UABR1,8)
#define MCF5272_RD_UART0_UABR2(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UABR2,8)
#define MCF5272_RD_UART0_UTFCSR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UTFCSR,8)
#define MCF5272_RD_UART0_URFCSR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_URFCSR,8)
#define MCF5272_RD_UART0_UIP(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART0_UIP,8)
#define MCF5272_RD_UART1_UMR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UMR,8)
#define MCF5272_RD_UART1_USR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_USR,8)
#define MCF5272_RD_UART1_URB(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UBUF,8)
#define MCF5272_RD_UART1_UCCR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UCCR,8)
#define MCF5272_RD_UART1_UISR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UISR,8)
#define MCF5272_RD_UART1_UABR1(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UABR1,8)
#define MCF5272_RD_UART1_UABR2(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UABR2,8)
#define MCF5272_RD_UART1_UTFCSR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UTFCSR,8)
#define MCF5272_RD_UART1_URFCSR(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_URFCSR,8)
#define MCF5272_RD_UART1_UIP(IMMP) \
Mcf5272_iord(IMMP,MCF5272_UART1_UIP,8)
/* Write access macros for general use */
#define MCF5272_WR_UART0_UMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UMR,8,DATA)
#define MCF5272_WR_UART0_UCSR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_USR,8,DATA)
#define MCF5272_WR_UART0_UCR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UCR,8,DATA)
#define MCF5272_WR_UART0_UTB(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UBUF,8,DATA)
#define MCF5272_WR_UART0_UACR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UCCR,8,DATA)
#define MCF5272_WR_UART0_UIMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UISR,8,DATA)
#define MCF5272_WR_UART0_UBG1(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UBG1,8,DATA)
#define MCF5272_WR_UART0_UBG2(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UBG2,8,DATA)
#define MCF5272_WR_UART0_UTFCSR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UTFCSR,8,DATA)
#define MCF5272_WR_UART0_URFCSR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_URFCSR,8,DATA)
#define MCF5272_WR_UART0_UOP1(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UOP1,8,DATA)
#define MCF5272_WR_UART0_UOP0(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART0_UOP0,8,DATA)
#define MCF5272_WR_UART1_UMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UMR,8,DATA)
#define MCF5272_WR_UART1_UCSR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_USR,8,DATA)
#define MCF5272_WR_UART1_UCR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UCR,8,DATA)
#define MCF5272_WR_UART1_UTB(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UBUF,8,DATA)
#define MCF5272_WR_UART1_UACR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UCCR,8,DATA)
#define MCF5272_WR_UART1_UIMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UISR,8,DATA)
#define MCF5272_WR_UART1_UBG1(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UBG1,8,DATA)
#define MCF5272_WR_UART1_UBG2(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UBG2,8,DATA)
#define MCF5272_WR_UART1_UTFCSR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UTFCSR,8,DATA)
#define MCF5272_WR_UART1_URFCSR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_URFCSR,8,DATA)
#define MCF5272_WR_UART1_UOP1(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UOP1,8,DATA)
#define MCF5272_WR_UART1_UOP0(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_UART1_UOP0,8,DATA)
/* Bit level definitions and macros */
#define MCF5272_UART_UMR1_RXRTS (0x80)
#define MCF5272_UART_UMR1_RXIRQ (0x40)
#define MCF5272_UART_UMR1_ERR (0x20)
#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5272_UART_UMR1_PM_NONE (0x10)
#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5272_UART_UMR1_PM_ODD (0x04)
#define MCF5272_UART_UMR1_PM_EVEN (0x00)
#define MCF5272_UART_UMR1_BC_5 (0x00)
#define MCF5272_UART_UMR1_BC_6 (0x01)
#define MCF5272_UART_UMR1_BC_7 (0x02)
#define MCF5272_UART_UMR1_BC_8 (0x03)
#define MCF5272_UART_UMR2_CM_NORMAL (0x00)
#define MCF5272_UART_UMR2_CM_ECHO (0x40)
#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5272_UART_UMR2_TXRTS (0x20)
#define MCF5272_UART_UMR2_TXCTS (0x10)
#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */
#define MCF5272_UART_USR_RB (0x80)
#define MCF5272_UART_USR_FE (0x40)
#define MCF5272_UART_USR_PE (0x20)
#define MCF5272_UART_USR_OE (0x10)
#define MCF5272_UART_USR_TXEMP (0x08)
#define MCF5272_UART_USR_TXRDY (0x04)
#define MCF5272_UART_USR_FFULL (0x02)
#define MCF5272_UART_USR_RXRDY (0x01)
#define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */
#define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */
#define MCF5272_UART_UCR_NONE (0x00)
#define MCF5272_UART_UCR_STOP_BREAK (0x70)
#define MCF5272_UART_UCR_START_BREAK (0x60)
#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5272_UART_UCR_RESET_ERROR (0x40)
#define MCF5272_UART_UCR_RESET_TX (0x30)
#define MCF5272_UART_UCR_RESET_RX (0x20)
#define MCF5272_UART_UCR_RESET_MR (0x10)
#define MCF5272_UART_UCR_TX_DISABLED (0x08)
#define MCF5272_UART_UCR_TX_ENABLED (0x04)
#define MCF5272_UART_UCR_RX_DISABLED (0x02)
#define MCF5272_UART_UCR_RX_ENABLED (0x01)
#define MCF5272_UART_UCCR_COS (0x10)
#define MCF5272_UART_UCCR_CTS (0x01)
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