📄 mcf5272.h
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/*
* File: MCF5272.h
* Purpose: MCF5272 definitions
*
* Notes:
*/
#ifndef _CPU_MCF5272_H
#define _CPU_MCF5272_H
/***********************************************************************/
/*
* Misc. Defines
*/
#ifdef FALSE
#undef FALSE
#endif
#define FALSE (0)
#ifdef TRUE
#undef TRUE
#endif
#define TRUE (1)
#ifdef NULL
#undef NULL
#endif
#define NULL (0)
/***********************************************************************/
/*
* The basic data types
*/
typedef volatile unsigned char vuint8; /* 8 bits */
typedef volatile unsigned short int vuint16; /* 16 bits */
typedef volatile unsigned long int vuint32; /* 32 bits */
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
/***********************************************************************/
/*
* Common M68K & ColdFire definitions
*/
#define ADDRESS uint32
#define INSTRUCTION uint16
#define ILLEGAL 0x4AFC
#define CPU_WORD_SIZE 16
/***********************************************************************/
/*
* Routines and macros for accessing Input/Output devices
*/
#define cpu_iord_8(ADDR) *((volatile uint8 *)(ADDR))
#define cpu_iord_16(ADDR) *((volatile uint16 *)(ADDR))
#define cpu_iord_32(ADDR) *((volatile uint32 *)(ADDR))
#define cpu_iowr_8(ADDR,DATA) *((volatile uint8 *)(ADDR)) = (DATA)
#define cpu_iowr_16(ADDR,DATA) *((volatile uint16 *)(ADDR)) = (DATA)
#define cpu_iowr_32(ADDR,DATA) *((volatile uint32 *)(ADDR)) = (DATA)
/***********************************************************************/
#define MCF5200_SR_T (0x8000)
#define MCF5200_SR_S (0x2000)
#define MCF5200_SR_M (0x1000)
#define MCF5200_SR_IPL (0x0700)
#define MCF5200_SR_IPL_0 (0x0000)
#define MCF5200_SR_IPL_1 (0x0100)
#define MCF5200_SR_IPL_2 (0x0200)
#define MCF5200_SR_IPL_3 (0x0300)
#define MCF5200_SR_IPL_4 (0x0400)
#define MCF5200_SR_IPL_5 (0x0500)
#define MCF5200_SR_IPL_6 (0x0600)
#define MCF5200_SR_IPL_7 (0x0700)
#define MCF5200_SR_X (0x0010)
#define MCF5200_SR_N (0x0008)
#define MCF5200_SR_Z (0x0004)
#define MCF5200_SR_V (0x0002)
#define MCF5200_SR_C (0x0001)
/***********************************************************************/
/*
* The ColdFire family of processors has a simplified exception stack
* frame that looks like the following:
*
* 3322222222221111 111111
* 1098765432109876 5432109876543210
* 8 +----------------+----------------+
* | Program Counter |
* 4 +----------------+----------------+
* |FS/Fmt/Vector/FS| SR |
* SP --> 0 +----------------+----------------+
*
* The stack self-aligns to a 4-byte boundary at an exception, with
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
* (SP += 0,1,2,3 bytes).
*/
#define MCF5200_RD_SF_FORMAT(PTR) \
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
#define MCF5200_RD_SF_VECTOR(PTR) \
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
#define MCF5200_RD_SF_FS(PTR) \
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
#define MCF5200_SF_SR(PTR) *((uint16 *)(PTR)+1)
#define MCF5200_SF_PC(PTR) *((uint32 *)(PTR)+1)
#if 0
typedef struct
{
uint16 SR;
uint16 FS_FMT_VECTOR_FS;
uint32 PC;
} MCF5200_STACK_FRAME;
#endif
/**********************************************************************
*
* Macro for computing address of on-chip peripheral registers
*
***********************************************************************/
#define Mcf5272_addr(IMMP,OFFSET) ((void *)&((uint8 *)IMMP)[OFFSET])
/**********************************************************************
*
* Macros for accessing the on-chip I/O resources
*
***********************************************************************/
#define Mcf5272_iord(IMMP,OFFSET,SIZE) \
*(volatile uint ## SIZE *)(Mcf5272_addr(IMMP,OFFSET))
#define Mcf5272_iowr(IMMP,OFFSET,SIZE,DATA) \
*(volatile uint ## SIZE *)(Mcf5272_addr(IMMP,OFFSET)) = (DATA)
/**********************************************************************
*
* CPU Space Registers
*
***********************************************************************/
/* Bit level definitions and macros */
#define MCF5272_CACR_CENB (0x80000000)
#define MCF5272_CACR_CFRZ (0x08000000)
#define MCF5272_CACR_CINV (0x01000000)
#define MCF5272_CACR_CMOD (0x00000200)
#define MCF5272_CACR_CWRP (0x00000020)
#define MCF5272_CACR_CLNF_00 (0x00000000)
#define MCF5272_CACR_CLNF_01 (0x00000001)
#define MCF5272_CACR_CLNF_10 (0x00000002)
#define MCF5272_ACR_BASE(a) ((a)&0xFF000000)
#define MCF5272_ACR_MASK(a) (((a)&0xFF000000) >> 8)
#define MCF5272_ACR_EN (0x00008000)
#define MCF5272_ACR_S_USER (0x00000000)
#define MCF5272_ACR_S_SUPER (0x00002000)
#define MCF5272_ACR_S_IGNORE (0x00006000)
#define MCF5272_ACR_ENIB (0x00000080)
#define MCF5272_ACR_CM (0x00000040)
#define MCF5272_ACR_WP (0x00000004)
#define MCF5272_SRAMBAR_BASE(a) ((a)&0xFFFFF000)
#define MCF5272_SRAMBAR_WP (0x00000100)
#define MCF5272_SRAMBAR_CI (0x00000020)
#define MCF5272_SRAMBAR_SC (0x00000010)
#define MCF5272_SRAMBAR_SD (0x00000008)
#define MCF5272_SRAMBAR_UC (0x00000004)
#define MCF5272_SRAMBAR_UD (0x00000002)
#define MCF5272_SRAMBAR_V (0x00000001)
#define MCF5272_ROMBAR_BASE(a) ((a)&0xFFFFF000)
#define MCF5272_ROMBAR_WP (0x00000100)
#define MCF5272_ROMBAR_CI (0x00000080)
#define MCF5272_ROMBAR_SC (0x00000040)
#define MCF5272_ROMBAR_SD (0x00000020)
#define MCF5272_ROMBAR_UC (0x00000004)
#define MCF5272_ROMBAR_UD (0x00000002)
#define MCF5272_ROMBAR_V (0x00000001)
#define MCF5272_MBAR_BASE(a) ((a)&0xFFFFFC00)
#define MCF5272_MBAR_SC (0x00000010)
#define MCF5272_MBAR_SD (0x00000008)
#define MCF5272_MBAR_UC (0x00000004)
#define MCF5272_MBAR_UD (0x00000002)
#define MCF5272_MBAR_V (0x00000001)
/**********************************************************************
*
* System Configuration Registers
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5272_SIM_MBAR (0x0000)
#define MCF5272_SIM_SCR (0x0004)
#define MCF5272_SIM_SPR (0x0006)
#define MCF5272_SIM_PMR (0x0008)
#define MCF5272_SIM_ALPR (0x000E)
#define MCF5272_SIM_DIR (0x0010)
/* Read access macros for general use */
#define MCF5272_RD_SIM_MBAR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_MBAR,32)
#define MCF5272_RD_SIM_SCR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_SCR,16)
#define MCF5272_RD_SIM_SPR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_SPR,16)
#define MCF5272_RD_SIM_PMR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PMR,32)
#define MCF5272_RD_SIM_DIR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_DIR,32)
/* Write access macros for general use */
#define MCF5272_WR_SIM_SCR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_SIM_SCR,16,DATA)
#define MCF5272_WR_SIM_SPR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_SIM_SPR,16,DATA)
#define MCF5272_WR_SIM_PMR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_SIM_PMR,32,DATA)
#define MCF5272_WR_SIM_ALPR(IMMP,DATA) \
Mcf5272_iowr(IMMP,MCF5272_SIM_ALPR,16,DATA)
/* Bit level definitions and macros */
#define MCF5272_SIM_SCR_HRST 0x1000
#define MCF5272_SIM_SCR_DRAMRST 0x3000
#define MCF5272_SIM_SCR_SWTR 0x2000
#define MCF5272_SIM_SCR_AR 0x0080
#define MCF5272_SIM_SCR_SOFT_RES 0x0040
#define MCF5272_SIM_SCR_HWWD_128 0x0000
#define MCF5272_SIM_SCR_HWWD_256 0x0001
#define MCF5272_SIM_SCR_HWWD_512 0x0002
#define MCF5272_SIM_SCR_HWWD_1024 0x0003
#define MCF5272_SIM_SCR_HWWD_2048 0x0004
#define MCF5272_SIM_SCR_HWWD_4096 0x0005
#define MCF5272_SIM_SCR_HWWD_8192 0x0006
#define MCF5272_SIM_SCR_HWWD_16384 0x0007
#define MCF5272_SIM_SPR_ADC 0x8000
#define MCF5272_SIM_SPR_ADCEN 0x0080
#define MCF5272_SIM_SPR_WPV 0x4000
#define MCF5272_SIM_SPR_WPVEN 0x0040
#define MCF5272_SIM_SPR_SMV 0x2000
#define MCF5272_SIM_SPR_SMVEN 0x0020
#define MCF5272_SIM_SPR_SBE 0x1000
#define MCF5272_SIM_SPR_SBEEN 0x0010
#define MCF5272_SIM_SPR_HWT 0x0800
#define MCF5272_SIM_SPR_HWTEN 0x0008
#define MCF5272_SIM_SPR_RPV 0x0400
#define MCF5272_SIM_SPR_RPVEN 0x0004
#define MCF5272_SIM_SPR_EXT 0x0200
#define MCF5272_SIM_SPR_EXTEN 0x0002
#define MCF5272_SIM_SPR_SUV 0x0100
#define MCF5272_SIM_SPR_SUVEN 0x0001
#define MCF5272_SIM_PMR_BDMPDN 0x80000000
#define MCF5272_SIM_PMR_ENETPDN 0x04000000
#define MCF5272_SIM_PMR_PLIPPDN 0x02000000
#define MCF5272_SIM_PMR_DRAMPDN 0x01000000
#define MCF5272_SIM_PMR_DMAPDN 0x00800000
#define MCF5272_SIM_PMR_PWMPDN 0x00400000
#define MCF5272_SIM_PMR_QSPIPDN 0x00200000
#define MCF5272_SIM_PMR_TIMERPDN 0x00100000
#define MCF5272_SIM_PMR_GPIOPDN 0x00080000
#define MCF5272_SIM_PMR_USBPDN 0x00040000
#define MCF5272_SIM_PMR_UART1PDN 0x00020000
#define MCF5272_SIM_PMR_UART0PDN 0x00010000
#define MCF5272_SIM_PMR_USBWK 0x00000400
#define MCF5272_SIM_PMR_UART1WK 0x00000200
#define MCF5272_SIM_PMR_UART0WK 0x00000100
#define MCF5272_SIM_PMR_MOS 0x00000020
#define MCF5272_SIM_PMR_SLPEN 0x00000010
/**********************************************************************
*
* Interrupt Controller Registers
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5272_SIM_ICR1 (0x0020)
#define MCF5272_SIM_ICR2 (0x0024)
#define MCF5272_SIM_ICR3 (0x0028)
#define MCF5272_SIM_ICR4 (0x002C)
#define MCF5272_SIM_ISR (0x0030)
#define MCF5272_SIM_PITR (0x0034)
#define MCF5272_SIM_PIWR (0x0038)
#define MCF5272_SIM_PIVR (0x003F)
/* Read access macros for general use */
#define MCF5272_RD_SIM_ICR1(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR1,32)
#define MCF5272_RD_SIM_ICR2(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR2,32)
#define MCF5272_RD_SIM_ICR3(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR3,32)
#define MCF5272_RD_SIM_ICR4(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR4,32)
#define MCF5272_RD_SIM_ISR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ISR,32)
#define MCF5272_RD_SIM_PITR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PITR,32)
#define MCF5272_RD_SIM_PIWR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PIWR,32)
#define MCF5272_RD_SIM_PIVR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PIVR,8)
/* Write access macros for general use */
#define MCF5272_WR_SIM_ICR1(IMMP,DATA) \
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