vga_register_file.v

周立功公司的SOPC源代码

/****************************************Copyright (c)**************************************************
**                               Guangzou ZLG-MCU Development Co.,LTD.
**                                      graduate school
**                                 http://www.zlgmcu.com
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			VGA_register_file.v
** Last modified Date:	2006-05-19
** Last Version:		1.0
** Descriptions:		VGA logic
**------------------------------------------------------------------------------------------------------
** Created by:			LiuYingbin
** Created date:		2006-03-24
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:		    RuiWenbin	
** Modified date:		2006-05-19
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module vga_register_file(	
	//Avalon Signals
	clock,
	reset_n, 
	chip_select,
	address,
	write,
	write_data,
	read,
	read_data,

	//VGA Interface Signals
	clk_100m,
	vga_addr,vga_req,vga_data,vga_ack,
	mouse_en,mouse_x,mouse_y,
	ico_wr_en,ico_wr_data,ico_wr_addr
	
);


		input 			clock;			    //System Clock
		input 			reset_n;			//System Reset
		input 			chip_select;		//Avalon Chip select signal
		input [19:0] 	address;	     	//Avalon Address bus 
		input 			write;				//Avalon Write signal
		input [31:0] 	write_data;			//Avalon Write data bus
		input 			read;			    //Avalon read signal
		output [31:0] 	read_data;	  		//Avalon read data bus

		input			clk_100m;
		output [18:0] 	vga_addr;
		output 	 		vga_req;
		output [7:0]	vga_data;
		input 	 		vga_ack;
		output 			mouse_en;
		output [9:0]	mouse_x;
		output [8:0]	mouse_y;
		output 			ico_wr_en;
		output [1:0]	ico_wr_data;
		output [9:0]	ico_wr_addr;


//Signal Declarations	
wire		write_act;
wire 		read_act;

reg [18:0]	vga_addr_r;
reg [18:0]  clr_addr_r;
reg [7:0]	write_data_r;
reg 		vga_ack_r;
reg			mouse_en_r;
reg [9:0]	mouse_x_r;
reg [8:0]	mouse_y_r;
reg			ico_wr_en_r;
reg	[1:0]	ico_wr_data_r;
reg [9:0]	ico_wr_addr_r;

reg			clr_vga_r;
reg			clr_over_r;

//determine if a vaild transaction was initiated 
assign write_act = chip_select & write;
assign read_act  = chip_select & read;

always @(posedge clock)
begin
    clr_vga_r <= 1'b0;
	if (write_act && ~clr_over_r)
	begin
		casez(address)
		
			20'b0???_????_????_????_????:         
			
		    begin
				vga_addr_r <= address[18:0];
				write_data_r <= write_data[7:0];
		    end

			20'b1000_????_????_????_????:         
	        begin
				ico_wr_addr_r <= address[9:0];
				ico_wr_data_r <= write_data[1:0];
				ico_wr_en_r <= 1'b1;
	        end

			20'b1001_0000_0000_0000_0000:
	        begin
				ico_wr_en_r <= 1'b0;
	        end        
	        
	   		20'b1010_0000_0000_0000_0000:
			begin
				mouse_x_r <= write_data[9:0];
				mouse_y_r <= write_data[18:10];		
			end
  
	   		20'b1011_0000_0000_0000_0000:
			begin
				mouse_en_r <= write_data[0];
			end	

            20'b1100_0000_0000_0000_0000:
            begin
				clr_vga_r <= 1'b1;
				write_data_r <= write_data[7:0]; 
            end
            
			default:;
		endcase
	end
end


always @(posedge clk_100m)
begin
	if(clr_vga_r || clr_over_r)
	begin
		clr_over_r <= 1'b1;
		if(vga_ack)
		clr_addr_r <= clr_addr_r + 1'b1;
		if(clr_addr_r[18:15] == 4'hf)
		begin
		    clr_over_r <= 1'b0;
			clr_addr_r <= 19'd0;
		end
	end
end


always @(posedge clk_100m)
begin
	if (vga_ack && ~clr_over_r)
		vga_ack_r <= 1'b1;
	else if (write_act)
		vga_ack_r <= 1'b0;
end


assign read_data = (read_act) ? {31'b0,vga_ack_r} : 32'b0;
assign vga_addr = (clr_over_r) ? clr_addr_r : vga_addr_r;
assign vga_req = 1'b1;
assign vga_data = write_data_r;
assign mouse_en = mouse_en_r;
assign mouse_x = mouse_x_r;
assign mouse_y = mouse_y_r;
assign ico_wr_en = ico_wr_en_r;
assign ico_wr_addr = ico_wr_addr_r;
assign ico_wr_data = ico_wr_data_r;

endmodule