vga_logic.vqm

周立功公司的SOPC源代码

defparam \sram_data[10]~I .oe_async_reset = "none";
defparam \sram_data[10]~I .input_sync_reset = "none";
defparam \sram_data[10]~I .output_sync_reset = "none";
defparam \sram_data[10]~I .oe_sync_reset = "none";
defparam \sram_data[10]~I .input_power_up = "low";
defparam \sram_data[10]~I .output_power_up = "low";
defparam \sram_data[10]~I .oe_power_up = "low";

cyclone_io \sram_data[11]~I (
	.datain(\wr_data[3]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[11]~4 ),
	.padio(sram_data[11]));
defparam \sram_data[11]~I .operation_mode = "bidir";
defparam \sram_data[11]~I .input_register_mode = "none";
defparam \sram_data[11]~I .output_register_mode = "none";
defparam \sram_data[11]~I .oe_register_mode = "none";
defparam \sram_data[11]~I .input_async_reset = "none";
defparam \sram_data[11]~I .output_async_reset = "none";
defparam \sram_data[11]~I .oe_async_reset = "none";
defparam \sram_data[11]~I .input_sync_reset = "none";
defparam \sram_data[11]~I .output_sync_reset = "none";
defparam \sram_data[11]~I .oe_sync_reset = "none";
defparam \sram_data[11]~I .input_power_up = "low";
defparam \sram_data[11]~I .output_power_up = "low";
defparam \sram_data[11]~I .oe_power_up = "low";

cyclone_io \sram_data[12]~I (
	.datain(\wr_data[4]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[12]~3 ),
	.padio(sram_data[12]));
defparam \sram_data[12]~I .operation_mode = "bidir";
defparam \sram_data[12]~I .input_register_mode = "none";
defparam \sram_data[12]~I .output_register_mode = "none";
defparam \sram_data[12]~I .oe_register_mode = "none";
defparam \sram_data[12]~I .input_async_reset = "none";
defparam \sram_data[12]~I .output_async_reset = "none";
defparam \sram_data[12]~I .oe_async_reset = "none";
defparam \sram_data[12]~I .input_sync_reset = "none";
defparam \sram_data[12]~I .output_sync_reset = "none";
defparam \sram_data[12]~I .oe_sync_reset = "none";
defparam \sram_data[12]~I .input_power_up = "low";
defparam \sram_data[12]~I .output_power_up = "low";
defparam \sram_data[12]~I .oe_power_up = "low";

cyclone_io \sram_data[13]~I (
	.datain(\wr_data[5]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[13]~2 ),
	.padio(sram_data[13]));
defparam \sram_data[13]~I .operation_mode = "bidir";
defparam \sram_data[13]~I .input_register_mode = "none";
defparam \sram_data[13]~I .output_register_mode = "none";
defparam \sram_data[13]~I .oe_register_mode = "none";
defparam \sram_data[13]~I .input_async_reset = "none";
defparam \sram_data[13]~I .output_async_reset = "none";
defparam \sram_data[13]~I .oe_async_reset = "none";
defparam \sram_data[13]~I .input_sync_reset = "none";
defparam \sram_data[13]~I .output_sync_reset = "none";
defparam \sram_data[13]~I .oe_sync_reset = "none";
defparam \sram_data[13]~I .input_power_up = "low";
defparam \sram_data[13]~I .output_power_up = "low";
defparam \sram_data[13]~I .oe_power_up = "low";

cyclone_io \sram_data[14]~I (
	.datain(\wr_data[6]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[14]~1 ),
	.padio(sram_data[14]));
defparam \sram_data[14]~I .operation_mode = "bidir";
defparam \sram_data[14]~I .input_register_mode = "none";
defparam \sram_data[14]~I .output_register_mode = "none";
defparam \sram_data[14]~I .oe_register_mode = "none";
defparam \sram_data[14]~I .input_async_reset = "none";
defparam \sram_data[14]~I .output_async_reset = "none";
defparam \sram_data[14]~I .oe_async_reset = "none";
defparam \sram_data[14]~I .input_sync_reset = "none";
defparam \sram_data[14]~I .output_sync_reset = "none";
defparam \sram_data[14]~I .oe_sync_reset = "none";
defparam \sram_data[14]~I .input_power_up = "low";
defparam \sram_data[14]~I .output_power_up = "low";
defparam \sram_data[14]~I .oe_power_up = "low";

cyclone_io \sram_data[15]~I (
	.datain(\wr_data[7]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[15]~0 ),
	.padio(sram_data[15]));
defparam \sram_data[15]~I .operation_mode = "bidir";
defparam \sram_data[15]~I .input_register_mode = "none";
defparam \sram_data[15]~I .output_register_mode = "none";
defparam \sram_data[15]~I .oe_register_mode = "none";
defparam \sram_data[15]~I .input_async_reset = "none";
defparam \sram_data[15]~I .output_async_reset = "none";
defparam \sram_data[15]~I .oe_async_reset = "none";
defparam \sram_data[15]~I .input_sync_reset = "none";
defparam \sram_data[15]~I .output_sync_reset = "none";
defparam \sram_data[15]~I .oe_sync_reset = "none";
defparam \sram_data[15]~I .input_power_up = "low";
defparam \sram_data[15]~I .output_power_up = "low";
defparam \sram_data[15]~I .oe_power_up = "low";

cyclone_io \clk_100m~I (
	.combout(\clk_100m~combout ),
	.padio(clk_100m));
defparam \clk_100m~I .operation_mode = "input";
defparam \clk_100m~I .input_register_mode = "none";
defparam \clk_100m~I .output_register_mode = "none";
defparam \clk_100m~I .oe_register_mode = "none";
defparam \clk_100m~I .input_async_reset = "none";
defparam \clk_100m~I .output_async_reset = "none";
defparam \clk_100m~I .oe_async_reset = "none";
defparam \clk_100m~I .input_sync_reset = "none";
defparam \clk_100m~I .output_sync_reset = "none";
defparam \clk_100m~I .oe_sync_reset = "none";
defparam \clk_100m~I .input_power_up = "low";
defparam \clk_100m~I .output_power_up = "low";
defparam \clk_100m~I .oe_power_up = "low";

cyclone_io \wr_addr[11]~I (
	.combout(\wr_addr[11]~combout ),
	.padio(wr_addr[11]));
defparam \wr_addr[11]~I .operation_mode = "input";
defparam \wr_addr[11]~I .input_register_mode = "none";
defparam \wr_addr[11]~I .output_register_mode = "none";
defparam \wr_addr[11]~I .oe_register_mode = "none";
defparam \wr_addr[11]~I .input_async_reset = "none";
defparam \wr_addr[11]~I .output_async_reset = "none";
defparam \wr_addr[11]~I .oe_async_reset = "none";
defparam \wr_addr[11]~I .input_sync_reset = "none";
defparam \wr_addr[11]~I .output_sync_reset = "none";
defparam \wr_addr[11]~I .oe_sync_reset = "none";
defparam \wr_addr[11]~I .input_power_up = "low";
defparam \wr_addr[11]~I .output_power_up = "low";
defparam \wr_addr[11]~I .oe_power_up = "low";

cyclone_io \wr_req~I (
	.combout(\wr_req~combout ),
	.padio(wr_req));
defparam \wr_req~I .operation_mode = "input";
defparam \wr_req~I .input_register_mode = "none";
defparam \wr_req~I .output_register_mode = "none";
defparam \wr_req~I .oe_register_mode = "none";
defparam \wr_req~I .input_async_reset = "none";
defparam \wr_req~I .output_async_reset = "none";
defparam \wr_req~I .oe_async_reset = "none";
defparam \wr_req~I .input_sync_reset = "none";
defparam \wr_req~I .output_sync_reset = "none";
defparam \wr_req~I .oe_sync_reset = "none";
defparam \wr_req~I .input_power_up = "low";
defparam \wr_req~I .output_power_up = "low";
defparam \wr_req~I .oe_power_up = "low";

cyclone_io \vga_reset~I (
	.combout(\vga_reset~combout ),
	.padio(vga_reset));
defparam \vga_reset~I .operation_mode = "input";
defparam \vga_reset~I .input_register_mode = "none";
defparam \vga_reset~I .output_register_mode = "none";
defparam \vga_reset~I .oe_register_mode = "none";
defparam \vga_reset~I .input_async_reset = "none";
defparam \vga_reset~I .output_async_reset = "none";
defparam \vga_reset~I .oe_async_reset = "none";
defparam \vga_reset~I .input_sync_reset = "none";
defparam \vga_reset~I .output_sync_reset = "none";
defparam \vga_reset~I .oe_sync_reset = "none";
defparam \vga_reset~I .input_power_up = "low";
defparam \vga_reset~I .output_power_up = "low";
defparam \vga_reset~I .oe_power_up = "low";

cyclone_lcell \sram_if:sram_if|state_next.read_addr~132_I (
	.datab(\sram_if:sram_if|timer[2] ),
	.datac(\sram_if:sram_if|timer[1] ),
	.datad(\sram_if:sram_if|timer[0] ),
	.combout(\sram_if:sram_if|state_next.read_addr~132 ));
defparam \sram_if:sram_if|state_next.read_addr~132_I .operation_mode = "normal";
defparam \sram_if:sram_if|state_next.read_addr~132_I .synch_mode = "off";
defparam \sram_if:sram_if|state_next.read_addr~132_I .register_cascade_mode = "off";
defparam \sram_if:sram_if|state_next.read_addr~132_I .sum_lutc_input = "datac";
defparam \sram_if:sram_if|state_next.read_addr~132_I .lut_mask = "0003";
defparam \sram_if:sram_if|state_next.read_addr~132_I .output_mode = "comb_only";

cyclone_lcell \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 (
	.clk(\clk_100m~combout ),
	.dataa(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[0] ),
	.datab(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|w1w ),
	.aclr(\vga_reset~combout ),
	.regout(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[0] ),
	.cout(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0~COUT ));
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 .operation_mode = "arithmetic";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 .synch_mode = "off";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 .register_cascade_mode = "off";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 .sum_lutc_input = "datac";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 .lut_mask = "66AA";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0 .output_mode = "reg_only";

cyclone_lcell \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 (
	.clk(\clk_100m~combout ),
	.dataa(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[1] ),
	.datab(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|w1w ),
	.aclr(\vga_reset~combout ),
	.cin(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella0~COUT ),
	.regout(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[1] ),
	.cout(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1~COUT ));
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 .operation_mode = "arithmetic";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 .synch_mode = "off";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 .register_cascade_mode = "off";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 .sum_lutc_input = "cin";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 .lut_mask = "6A5F";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1 .output_mode = "reg_only";

cyclone_lcell \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 (
	.clk(\clk_100m~combout ),
	.dataa(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[2] ),
	.datab(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|w1w ),
	.aclr(\vga_reset~combout ),
	.cin(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella1~COUT ),
	.regout(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[2] ),
	.cout(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2~COUT ));
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 .operation_mode = "arithmetic";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 .synch_mode = "off";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 .register_cascade_mode = "off";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 .sum_lutc_input = "cin";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 .lut_mask = "A60A";
defparam \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2 .output_mode = "reg_only";

cyclone_lcell \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella3 (
	.clk(\clk_100m~combout ),
	.dataa(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|w1w ),
	.datab(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q[3] ),
	.aclr(\vga_reset~combout ),
	.cin(\fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|counter_cella2~COUT ),
	.regout(\fi