vga_logic.vqm

周立功公司的SOPC源代码

wire \wr_data[7]~combout ;
wire \data_to_sram:data_to_sram|sram_data~102 ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|dffe5a ;
wire [18:0] \arb_module:arb_module|arbrd_addr_r ;
wire [8:0] \ico_module:ico_module|y_inc_r ;
wire [7:0] \sram_if:sram_if|rd_data_r ;
wire [9:0] \vga_disp:vga_disp|hcount ;
wire [1:0] \ico_ram:ico_ram|altsyncram:altsyncram_component|altsyncram_6ic1:auto_generated|q_b ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|dffe7a ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|dpram_fcr:dpram4|altsyncram_0cc1:altsyncram14|q_b ;
wire [9:0] \vga_disp:vga_disp|vcount ;
wire [7:0] \ico_module:ico_module|data_out_r ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|dffe8a ;
wire [2:0] \sram_if:sram_if|timer ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cntr_9v7:cntr1|safe_q ;
wire [1:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cs10a ;
wire [9:0] \ico_module:ico_module|ico_rd_addr_r ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|dffe9a ;
wire [7:0] \fifo:fifo|dcfifo:dcfifo_component|dcfifo_rt21:auto_generated|alt_sync_fifo_idm:sync_fifo|cs12a ;
wire [9:0] \ico_module:ico_module|x_inc_r ;

wire \sram_if:sram_if|__ALT_INV__state.write_addr ;
wire \sram_if:sram_if|__ALT_INV__sram_rd_r~0 ;
wire \sram_if:sram_if|__ALT_INV__sram_addr[18]~783 ;

wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;

assign \sram_if:sram_if|__ALT_INV__state.write_addr  = ~ \sram_if:sram_if|state.write_addr ;
assign \sram_if:sram_if|__ALT_INV__sram_rd_r~0  = ~ \sram_if:sram_if|sram_rd_r~0 ;
assign \sram_if:sram_if|__ALT_INV__sram_addr[18]~783  = ~ \sram_if:sram_if|sram_addr[18]~783 ;

cyclone_io \sram_data[0]~I (
	.datain(\wr_data[0]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[0]~15 ),
	.padio(sram_data[0]));
defparam \sram_data[0]~I .operation_mode = "bidir";
defparam \sram_data[0]~I .input_register_mode = "none";
defparam \sram_data[0]~I .output_register_mode = "none";
defparam \sram_data[0]~I .oe_register_mode = "none";
defparam \sram_data[0]~I .input_async_reset = "none";
defparam \sram_data[0]~I .output_async_reset = "none";
defparam \sram_data[0]~I .oe_async_reset = "none";
defparam \sram_data[0]~I .input_sync_reset = "none";
defparam \sram_data[0]~I .output_sync_reset = "none";
defparam \sram_data[0]~I .oe_sync_reset = "none";
defparam \sram_data[0]~I .input_power_up = "low";
defparam \sram_data[0]~I .output_power_up = "low";
defparam \sram_data[0]~I .oe_power_up = "low";

cyclone_io \sram_data[1]~I (
	.datain(\wr_data[1]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[1]~14 ),
	.padio(sram_data[1]));
defparam \sram_data[1]~I .operation_mode = "bidir";
defparam \sram_data[1]~I .input_register_mode = "none";
defparam \sram_data[1]~I .output_register_mode = "none";
defparam \sram_data[1]~I .oe_register_mode = "none";
defparam \sram_data[1]~I .input_async_reset = "none";
defparam \sram_data[1]~I .output_async_reset = "none";
defparam \sram_data[1]~I .oe_async_reset = "none";
defparam \sram_data[1]~I .input_sync_reset = "none";
defparam \sram_data[1]~I .output_sync_reset = "none";
defparam \sram_data[1]~I .oe_sync_reset = "none";
defparam \sram_data[1]~I .input_power_up = "low";
defparam \sram_data[1]~I .output_power_up = "low";
defparam \sram_data[1]~I .oe_power_up = "low";

cyclone_io \sram_data[2]~I (
	.datain(\wr_data[2]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[2]~13 ),
	.padio(sram_data[2]));
defparam \sram_data[2]~I .operation_mode = "bidir";
defparam \sram_data[2]~I .input_register_mode = "none";
defparam \sram_data[2]~I .output_register_mode = "none";
defparam \sram_data[2]~I .oe_register_mode = "none";
defparam \sram_data[2]~I .input_async_reset = "none";
defparam \sram_data[2]~I .output_async_reset = "none";
defparam \sram_data[2]~I .oe_async_reset = "none";
defparam \sram_data[2]~I .input_sync_reset = "none";
defparam \sram_data[2]~I .output_sync_reset = "none";
defparam \sram_data[2]~I .oe_sync_reset = "none";
defparam \sram_data[2]~I .input_power_up = "low";
defparam \sram_data[2]~I .output_power_up = "low";
defparam \sram_data[2]~I .oe_power_up = "low";

cyclone_io \sram_data[3]~I (
	.datain(\wr_data[3]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[3]~12 ),
	.padio(sram_data[3]));
defparam \sram_data[3]~I .operation_mode = "bidir";
defparam \sram_data[3]~I .input_register_mode = "none";
defparam \sram_data[3]~I .output_register_mode = "none";
defparam \sram_data[3]~I .oe_register_mode = "none";
defparam \sram_data[3]~I .input_async_reset = "none";
defparam \sram_data[3]~I .output_async_reset = "none";
defparam \sram_data[3]~I .oe_async_reset = "none";
defparam \sram_data[3]~I .input_sync_reset = "none";
defparam \sram_data[3]~I .output_sync_reset = "none";
defparam \sram_data[3]~I .oe_sync_reset = "none";
defparam \sram_data[3]~I .input_power_up = "low";
defparam \sram_data[3]~I .output_power_up = "low";
defparam \sram_data[3]~I .oe_power_up = "low";

cyclone_io \sram_data[4]~I (
	.datain(\wr_data[4]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[4]~11 ),
	.padio(sram_data[4]));
defparam \sram_data[4]~I .operation_mode = "bidir";
defparam \sram_data[4]~I .input_register_mode = "none";
defparam \sram_data[4]~I .output_register_mode = "none";
defparam \sram_data[4]~I .oe_register_mode = "none";
defparam \sram_data[4]~I .input_async_reset = "none";
defparam \sram_data[4]~I .output_async_reset = "none";
defparam \sram_data[4]~I .oe_async_reset = "none";
defparam \sram_data[4]~I .input_sync_reset = "none";
defparam \sram_data[4]~I .output_sync_reset = "none";
defparam \sram_data[4]~I .oe_sync_reset = "none";
defparam \sram_data[4]~I .input_power_up = "low";
defparam \sram_data[4]~I .output_power_up = "low";
defparam \sram_data[4]~I .oe_power_up = "low";

cyclone_io \sram_data[5]~I (
	.datain(\wr_data[5]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[5]~10 ),
	.padio(sram_data[5]));
defparam \sram_data[5]~I .operation_mode = "bidir";
defparam \sram_data[5]~I .input_register_mode = "none";
defparam \sram_data[5]~I .output_register_mode = "none";
defparam \sram_data[5]~I .oe_register_mode = "none";
defparam \sram_data[5]~I .input_async_reset = "none";
defparam \sram_data[5]~I .output_async_reset = "none";
defparam \sram_data[5]~I .oe_async_reset = "none";
defparam \sram_data[5]~I .input_sync_reset = "none";
defparam \sram_data[5]~I .output_sync_reset = "none";
defparam \sram_data[5]~I .oe_sync_reset = "none";
defparam \sram_data[5]~I .input_power_up = "low";
defparam \sram_data[5]~I .output_power_up = "low";
defparam \sram_data[5]~I .oe_power_up = "low";

cyclone_io \sram_data[6]~I (
	.datain(\wr_data[6]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[6]~9 ),
	.padio(sram_data[6]));
defparam \sram_data[6]~I .operation_mode = "bidir";
defparam \sram_data[6]~I .input_register_mode = "none";
defparam \sram_data[6]~I .output_register_mode = "none";
defparam \sram_data[6]~I .oe_register_mode = "none";
defparam \sram_data[6]~I .input_async_reset = "none";
defparam \sram_data[6]~I .output_async_reset = "none";
defparam \sram_data[6]~I .oe_async_reset = "none";
defparam \sram_data[6]~I .input_sync_reset = "none";
defparam \sram_data[6]~I .output_sync_reset = "none";
defparam \sram_data[6]~I .oe_sync_reset = "none";
defparam \sram_data[6]~I .input_power_up = "low";
defparam \sram_data[6]~I .output_power_up = "low";
defparam \sram_data[6]~I .oe_power_up = "low";

cyclone_io \sram_data[7]~I (
	.datain(\wr_data[7]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~101 ),
	.combout(\sram_data[7]~8 ),
	.padio(sram_data[7]));
defparam \sram_data[7]~I .operation_mode = "bidir";
defparam \sram_data[7]~I .input_register_mode = "none";
defparam \sram_data[7]~I .output_register_mode = "none";
defparam \sram_data[7]~I .oe_register_mode = "none";
defparam \sram_data[7]~I .input_async_reset = "none";
defparam \sram_data[7]~I .output_async_reset = "none";
defparam \sram_data[7]~I .oe_async_reset = "none";
defparam \sram_data[7]~I .input_sync_reset = "none";
defparam \sram_data[7]~I .output_sync_reset = "none";
defparam \sram_data[7]~I .oe_sync_reset = "none";
defparam \sram_data[7]~I .input_power_up = "low";
defparam \sram_data[7]~I .output_power_up = "low";
defparam \sram_data[7]~I .oe_power_up = "low";

cyclone_io \sram_data[8]~I (
	.datain(\wr_data[0]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[8]~7 ),
	.padio(sram_data[8]));
defparam \sram_data[8]~I .operation_mode = "bidir";
defparam \sram_data[8]~I .input_register_mode = "none";
defparam \sram_data[8]~I .output_register_mode = "none";
defparam \sram_data[8]~I .oe_register_mode = "none";
defparam \sram_data[8]~I .input_async_reset = "none";
defparam \sram_data[8]~I .output_async_reset = "none";
defparam \sram_data[8]~I .oe_async_reset = "none";
defparam \sram_data[8]~I .input_sync_reset = "none";
defparam \sram_data[8]~I .output_sync_reset = "none";
defparam \sram_data[8]~I .oe_sync_reset = "none";
defparam \sram_data[8]~I .input_power_up = "low";
defparam \sram_data[8]~I .output_power_up = "low";
defparam \sram_data[8]~I .oe_power_up = "low";

cyclone_io \sram_data[9]~I (
	.datain(\wr_data[1]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[9]~6 ),
	.padio(sram_data[9]));
defparam \sram_data[9]~I .operation_mode = "bidir";
defparam \sram_data[9]~I .input_register_mode = "none";
defparam \sram_data[9]~I .output_register_mode = "none";
defparam \sram_data[9]~I .oe_register_mode = "none";
defparam \sram_data[9]~I .input_async_reset = "none";
defparam \sram_data[9]~I .output_async_reset = "none";
defparam \sram_data[9]~I .oe_async_reset = "none";
defparam \sram_data[9]~I .input_sync_reset = "none";
defparam \sram_data[9]~I .output_sync_reset = "none";
defparam \sram_data[9]~I .oe_sync_reset = "none";
defparam \sram_data[9]~I .input_power_up = "low";
defparam \sram_data[9]~I .output_power_up = "low";
defparam \sram_data[9]~I .oe_power_up = "low";

cyclone_io \sram_data[10]~I (
	.datain(\wr_data[2]~combout ),
	.oe(\data_to_sram:data_to_sram|sram_data~102 ),
	.combout(\sram_data[10]~5 ),
	.padio(sram_data[10]));
defparam \sram_data[10]~I .operation_mode = "bidir";
defparam \sram_data[10]~I .input_register_mode = "none";
defparam \sram_data[10]~I .output_register_mode = "none";
defparam \sram_data[10]~I .oe_register_mode = "none";
defparam \sram_data[10]~I .input_async_reset = "none";
defparam \sram_data[10]~I .output_async_reset = "none";