vga_avalon_interface.v

周立功公司的SOPC源代码

/****************************************Copyright (c)**************************************************
**                               Guangzou ZLG-MCU Development Co.,LTD.
**                                      graduate school
**                                 http://www.zlgmcu.com
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			vga_avalon_interface.v
** Last modified Date:	2006-03-24
** Last Version:		1.0
** Descriptions:		VGA logic
**------------------------------------------------------------------------------------------------------
** Created by:			LiuYingbin
** Created date:		2006-03-24
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:		    RuiWenBin	
** Modified date:		2006-05-17
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module vga_avalon_interface(
	//Avalon Signals
	clock,
	reset_n,
	chip_select,
	address,
	write,
	write_data,
	read,
	read_data,
	
	//PWM Output Signals
	clk_100m,clk_25m,
	sram_nwe,sram_noe,sram_addr,sram_data,upper_byte,lower_byte,sram_ncs,
	hsync,vsync,disp_dato
 );

		//Avalon_Slave_PWM Avalon I/O
		input 			clock;		 	//System clock - tied to all blocks
		input 			reset_n;		//System reset - tied to all blocks
		input 			chip_select;	//Avalon Chip select
		input [19:0]	address;	    //Avalon Address bus 
		input 			write;			//Avalon Write signal
		input [31:0]	write_data;		//Avalon Write data bus
		input 			read;		    //Avalon Read signal
			
		output [31:0]	read_data;		//Avalon Read data bus
		
		//Avalon_Slave
		input 			clk_100m;
		input 			clk_25m;
		
		output 			sram_nwe;
		output 			sram_noe;
		output 	[17:0] 	sram_addr;			
		inout   [15:0]	sram_data;
		output			upper_byte;
		output			lower_byte;
		output			sram_ncs;
	
		output 			hsync;
		output 			vsync;
		output 	[7:0] 	disp_dato;

wire			vga_reset;
wire			vga_req;
wire [18:0] 	vga_addr;
wire [7:0]		vga_data;
wire			vga_ack;
wire			mouse_en;
wire [9:0]      mouse_x;
wire [8:0]		mouse_y;
wire			ico_wr_en;
wire [9:0]		ico_wr_addr;
wire [1:0]		ico_wr_data;
	
assign vga_reset = ~reset_n;
assign sram_ncs = 1'b0;

//VGA Instance
vga_logic 	u1(
			.clk_100m(clk_100m),
			.clk_25m(clk_25m),
			.vga_reset(vga_reset),
			.wr_req(vga_req),
			.wr_addr(vga_addr),
			.wr_data(vga_data),
			.wr_ack(vga_ack),
			.ico_wr_clk(clock),
			.ico_wr_en(ico_wr_en),
			.ico_wr_addr(ico_wr_addr),
			.ico_wr_data(ico_wr_data),
			.mouse_en(mouse_en),
			.mouse_x(mouse_x),
			.mouse_y(mouse_y),
			.sram_nwe(sram_nwe),
			.sram_noe(sram_noe),
			.sram_addr(sram_addr),
			.sram_data(sram_data),
			.upper_byte(upper_byte),
			.lower_byte(lower_byte),
			.hsync(hsync),
			.vsync(vsync),
			.disp_dato(disp_dato)
			);
			
	
//Register File instance
vga_register_file U2(	
		.clock(clock),
		.reset_n(reset_n),
		.chip_select(chip_select),
		.address(address),
		.write(write),
		.write_data(write_data),
		.read(read),
		.read_data(read_data),
		//********************
		.clk_100m(clk_100m),
		.vga_addr(vga_addr),
		.vga_req(vga_req),
		.vga_data(vga_data),
		.vga_ack(vga_ack),
		.mouse_en(mouse_en),
		.mouse_x(mouse_x),
		.mouse_y(mouse_y),
		.ico_wr_en(ico_wr_en),
		.ico_wr_data(ico_wr_data),
		.ico_wr_addr(ico_wr_addr)
		);

endmodule