vga.v

来自「周立功公司的SOPC源代码」· Verilog 代码 · 共 102 行

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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module vga (
             // inputs:
              address,
              chip_select,
              clk_100m,
              clk_25m,
              clock,
              read,
              reset_n,
              write,
              write_data,

             // outputs:
              disp_dato,
              hsync,
              lower_byte,
              read_data,
              sram_addr,
              sram_data,
              sram_ncs,
              sram_noe,
              sram_nwe,
              upper_byte,
              vsync
           );

  output  [  7: 0] disp_dato;
  output           hsync;
  output           lower_byte;
  output  [ 31: 0] read_data;
  output  [ 17: 0] sram_addr;
  inout   [ 15: 0] sram_data;
  output           sram_ncs;
  output           sram_noe;
  output           sram_nwe;
  output           upper_byte;
  output           vsync;
  input   [ 19: 0] address;
  input            chip_select;
  input            clk_100m;
  input            clk_25m;
  input            clock;
  input            read;
  input            reset_n;
  input            write;
  input   [ 31: 0] write_data;

  wire    [  7: 0] disp_dato;
  wire             hsync;
  wire             lower_byte;
  wire    [ 31: 0] read_data;
  wire    [ 17: 0] sram_addr;
  wire    [ 15: 0] sram_data;
  wire             sram_ncs;
  wire             sram_noe;
  wire             sram_nwe;
  wire             upper_byte;
  wire             vsync;
  vga_avalon_interface the_vga_avalon_interface
    (
      .address     (address),
      .chip_select (chip_select),
      .clk_100m    (clk_100m),
      .clk_25m     (clk_25m),
      .clock       (clock),
      .disp_dato   (disp_dato),
      .hsync       (hsync),
      .lower_byte  (lower_byte),
      .read        (read),
      .read_data   (read_data),
      .reset_n     (reset_n),
      .sram_addr   (sram_addr),
      .sram_data   (sram_data),
      .sram_ncs    (sram_ncs),
      .sram_noe    (sram_noe),
      .sram_nwe    (sram_nwe),
      .upper_byte  (upper_byte),
      .vsync       (vsync),
      .write       (write),
      .write_data  (write_data)
    );



endmodule