keyboard_register_file.v

周立功公司的SOPC源代码

/****************************************Copyright (c)**************************************************
**                               Guangzou ZLG-MCU Development Co.,LTD.
**                                      graduate school
**                                 http://www.zlgmcu.com
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			keyboard_avalon_interface.v
** Last modified Date:	2006-04-14
** Last Version:		1.0
** Descriptions:		keyboard logic
**------------------------------------------------------------------------------------------------------
** Created by:			RuiWenBin
** Created date:		2006-04-14
** Version:				1.0
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
** Modified by:		
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module keyboard_register_file(	
	//Avalon Signals
	clock,
	reset_n, 
	chip_select,
	address,
	write,
	write_data,
	read,
	read_data,
	interrupt,
    
    //ps2_keyboard_interface signals
	rx_extended,
	rx_released,
	rx_shift_key_on,
	rx_scan_code,
	rx_ascii,
	rx_data_ready,
	tx_write_ack,
	tx_error_no_keyboard_ack,
	tx_data,
	tx_write,
	rx_read,
	reset
);


		input 			clock;			    //System Clock
		input 			reset_n;			//System Reset
		input 			chip_select;		//Avalon Chip select signal
		input		 	address;	     	//Avalon Address bus 
		input 			write;				//Avalon Write signal
		input [31:0] 	write_data;			//Avalon Write data bus
		input 			read;			    //Avalon read signal
		output [31:0] 	read_data;	  		//Avalon read data bus
		output			interrupt;			//System Interrupt;

		input			rx_extended;
		input			rx_released;
		input			rx_shift_key_on;
		input[7:0]		rx_scan_code;
		input[7:0]		rx_ascii;
		input			rx_data_ready;
		input			tx_write_ack;
		input			tx_error_no_keyboard_ack;
		output[7:0]		tx_data;
		output			tx_write;
		output			rx_read;
		output			reset;
		

//Signal Declarations	
reg[7:0]	tx_data_r;
reg			tx_write_r;
reg			tx_write_r1;
reg 			tx_error_r;
reg [31:0] 	read_data_r;			//Read_data bus

wire		write_act;
wire		read_act;
wire		write_word_act;


//determine if a vaild transaction was initiated 
assign write_act = chip_select & write;		
assign read_act  = chip_select & read;

assign rx_read = read_act && (address == rd_data);    //Read data
assign tx_write = tx_write_r;
assign read_data = read_data_r;
assign tx_data = tx_data_r;
assign reset = ~reset_n;

assign interrupt = rx_data_ready || tx_error_r;

parameter		rd_data 		= 1'b0,
				wr_word 		= 1'b1;


always @(posedge clock)
begin
	if(tx_error_no_keyboard_ack)
		tx_error_r <= 1'b1;
	else if(write_act && (address == wr_word))
		tx_error_r <= 1'b0;
		
end

always @(posedge clock)
begin
	if(write_act && (address == wr_word))
	begin
		tx_write_r <= 1'b1;
	end   
	else if(tx_write_ack)
	begin
		tx_write_r1 <= 1'b1;
	end   
	else if(tx_write_r1)   
	begin
		tx_write_r <= 1'b0;
		tx_write_r1 <= 1'b0;
	end 
end

//write
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)
	begin
		tx_data_r <= 8'hf4;
	end
	else if (write_act)
	begin
		case (address)
			wr_word:
			begin
				tx_data_r <= write_data[7:0];
			end

			default:
			begin
			end 
		endcase 
	end 
end             
 
//read               
always @(read_act 
		or address  
		or tx_error_r
		or rx_extended
		or rx_released
		or rx_shift_key_on
		or rx_data_ready
		or rx_scan_code
		or rx_ascii)
begin           
	if (read_act)
	begin       
		case (address)			
			rd_data:
			begin
				read_data_r <= {11'b0,
								tx_error_r,       //1 bit	
								rx_extended,      //1 bit
								rx_released,      //1 bit
								rx_shift_key_on,  //1 bit
								rx_data_ready,    //1 bit
								rx_scan_code,     //8 bits
								rx_ascii};        //8 bits				
			end
		
			default:
			begin
				read_data_r <= 32'h0;
			end
		endcase
	end
	else
		read_data_r <= 32'h0;
end


endmodule