nios2e_1c6.ptf.bak

周立功公司的SOPC源代码

            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_dq
            {
               Is_Enabled = "1";
               direction = "inout";
               width = "16";
            }
            PORT zs_dqm
            {
               Is_Enabled = "1";
               direction = "input";
               width = "2";
            }
            PORT zs_ras_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_we_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.v, __PROJECT_DIRECTORY__/sdram_test_component.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sysid
   {
      class = "altera_avalon_sysid";
      class_version = "4.0";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "1";
            Data_Width = "32";
            Base_Address = "0x00A00838";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Read_Latency = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "System ID (at last Generate):<br> <b>D8785102</b>    (unique ID tag) <br> <b>446E6C45</b> (timestamp: Sat May 20, 2006 @9:09 AM)";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         id = "3631763714u";
         timestamp = "1148087365u";
         MAKE 
         {
            TARGET verifysysid
            {
               verifysysid 
               {
                  All_Depends_On = "0";
                  Command = "nios2-download $(JTAG_CABLE)                                --sidp=0x00A00838 --id=3631763714 --timestamp=1148087365";
                  Is_Phony = "1";
                  Target_File = "dummy_verifysysid_file";
               }
            }
         }
      }
   }
   MODULE vga
   {
      class = "zlg_avalon_vga";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Is_Enabled = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL x101
            {
               name = "zlg_avalon_vga/global_signals";
               format = "Divider";
            }
            SIGNAL x102
            {
               name = "zlg_avalon_vga/avalon_slave_0";
               format = "Divider";
            }
            SIGNAL x103
            {
               name = "clock";
            }
            SIGNAL x104
            {
               name = "reset_n";
            }
            SIGNAL x105
            {
               name = "chip_select";
            }
            SIGNAL x106
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL x107
            {
               name = "write";
            }
            SIGNAL x108
            {
               name = "write_data";
               radix = "hexadecimal";
            }
            SIGNAL x109
            {
               name = "read";
            }
            SIGNAL x110
            {
               name = "clk_100m";
            }
            SIGNAL x111
            {
               name = "clk_25m";
            }
            SIGNAL x112
            {
               name = "read_data";
               radix = "hexadecimal";
            }
            SIGNAL x113
            {
               name = "sram_nwe";
            }
            SIGNAL x114
            {
               name = "sram_noe";
            }
            SIGNAL x115
            {
               name = "sram_addr";
               radix = "hexadecimal";
            }
            SIGNAL x116
            {
               name = "upper_byte";
            }
            SIGNAL x117
            {
               name = "lower_byte";
            }
            SIGNAL x118
            {
               name = "hsync";
            }
            SIGNAL x119
            {
               name = "vsync";
            }
            SIGNAL x120
            {
               name = "disp_dato";
               radix = "hexadecimal";
            }
            SIGNAL x121
            {
               name = "sram_data";
               radix = "hexadecimal";
            }
            SIGNAL x122
            {
               name = "sram_ncs";
            }
         }
      }
      SLAVE avalon_slave_0
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Width = "20";
            Address_Alignment = "native";
            Data_Width = "32";
            Has_Base_Address = "1";
            Has_IRQ = "0";
            Setup_Time = "0cycles";
            Hold_Time = "0cycles";
            Read_Wait_States = "0cycles";
            Write_Wait_States = "0cycles";
            Read_Latency = "0";
            Maximum_Pending_Read_Transactions = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Base_Address = "0x00C00000";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "0";
               Write_Wait_Value = "0";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "native";
               Is_Printable_Device = "0";
               interface_name = "Avalon Slave";
               Minimum_Arbitration_Shares = "1";
               external_wait = "0";
               Is_Memory_Device = "0";
            }
         }
         PORT_WIRING 
         {
            PORT clock
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "clk";
               is_shared = "0";
            }
            PORT reset_n
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "reset_n";
               is_shared = "0";
            }
            PORT chip_select
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect";
               is_shared = "0";
            }
            PORT address
            {
               width = "20";
               width_expression = "";
               direction = "input";
               type = "address";
               is_shared = "0";
            }
            PORT write
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write";
               is_shared = "0";
            }
            PORT write_data
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
            }
            PORT read
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "read";
               is_shared = "0";
            }
            PORT clk_100m
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "export";
               is_shared = "0";
            }
            PORT clk_25m
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "export";
               is_shared = "0";
            }
            PORT read_data
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
            }
            PORT sram_nwe
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT sram_noe
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT sram_addr
            {
               width = "18";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT upper_byte
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT lower_byte
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT hsync
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT vsync
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT disp_dato
            {
               width = "8";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
            }
            PORT sram_data
            {
               width = "16";
               width_expression = "";
               direction = "inout";