vportcap1.c

基于DM642

		VP_FSETH(vpCaptureHandle, VCACTL, SFDE, VP_VCACTL_SFDE_ENABLE);
		/* Set last pixel to be captured in Field1 (VCA_STOP1 reg) */
		VP_RSETH(vpCaptureHandle, VCASTOP1,
		VP_VCASTOP1_RMK(VCA_YSTOP1, VCA_XSTOP1));
		/* Set last pixel to be captured in Field2 (VCA_STOP2 reg) */
		VP_RSETH(vpCaptureHandle, VCASTOP2,VP_VCASTOP2_RMK(VCA_YSTOP2, VCA_XSTOP2));
		/* Set first pixel to be captured in Field1 (VCA_STRT1 reg) */
		VP_RSETH(vpCaptureHandle, VCASTRT1, VP_VCASTRT1_RMK(VCA_YSTART1,	VP_VCASTRT1_SSE_ENABLE, VCA_XSTART1));
		/* Set first pixel to be captured in Field2 (VCA_STRT2 reg) */
		VP_RSETH(vpCaptureHandle, VCASTRT2,
		VP_VCASTRT2_RMK(VCA_YSTART2, VCA_XSTART2));
		/* Set threshold values */
		VP_RSETH(vpCaptureHandle, VCATHRLD,
		VP_VCATHRLD_RMK(VCA_THRLD_FIELD2, VCA_THRLD_FIELD1));
		/* Set capture event-register values */
		VP_RSETH(vpCaptureHandle, VCAEVTCT,
		VP_VCAEVTCT_RMK(VCA_CAPEVT2,VCA_CAPEVT1));
		/* Vertical interrupts (VCA_INT) are not enabled in this */
		/* in this example- */
		/* Set CMODE to 8-bit BT-656 */
		VP_FSETH(vpCaptureHandle, VCACTL, CMODE, VP_VCACTL_CMODE_BT656B);
		/* Set non-continuous frame capture */
		VP_FSETH(vpCaptureHandle, VCACTL, CON, VP_VCACTL_CON_DISABLE);
		VP_FSETH(vpCaptureHandle, VCACTL, FRAME, VP_VCACTL_FRAME_FRMCAP);
		VP_FSETH(vpCaptureHandle, VCACTL, CF2, VP_VCACTL_CF2_NONE);
		VP_FSETH(vpCaptureHandle, VCACTL, CF1, VP_VCACTL_CF1_NONE);
		/* Let FDD and FINV to be their defaults */
		/* Set VRST to end of vertical blanking */
		VP_FSETH(vpCaptureHandle, VCACTL, VRST, VP_VCACTL_VRST_V0EAV);
		/* Set HRST to start of horizontal blanking */
		VP_FSETH(vpCaptureHandle, VCACTL, HRST, VP_VCACTL_HRST_EAV);
		/* 10-bit pack mode(10BPK bit) in this 8-bit example */
		/* No (1/2) scaling and no chroma re-sampling in this example */
		/* Enable video port interrupts */
		IRQ_enable(vpCaptureHandle->eventId);
		/* Setup Y, Cb and Cr EDMA channels */
		setupVPCapChaAEDMA(portNumber);
		/* Clear VPHLT in VP_CTL to make video port function */
		VP_FSETH(vpCaptureHandle, VPCTL, VPHLT, VP_VPCTL_VPHLT_CLEAR);
		/* -------------- */
		/* enable capture */
		/* -------------- */
		/* set VCEN bit to enable capture */
		VP_FSETH(vpCaptureHandle, VCACTL, VCEN, VP_VCACTL_VCEN_ENABLE);
		/* clear BLKCAP in VCA_CTL to enable capture DMA events */
		VP_FSETH(vpCaptureHandle, VCACTL, BLKCAP,VP_VCACTL_BLKCAP_CLEAR);

		return vpCaptureHandle;
}
/*---------------------------------------------------------------- */
/* Function : VPCapChaAIsr */
/* Description : This capture ISR clears FRMC to continue capture */
/* in this non-continuous mode and also clears other */
/* status bits- */
/*---------------------------------------------------------------- */
interrupt void cap1(void)
{
		Uint32 vpis = 0;
		/* Get video port status register value */
		vpis = VP_RGETH(vpCaptureHandle, VPIS);
		if(vpis & _VP_VPIS_CCMPA_MASK) /* capture complete */
		{
			/* Clear frame complete bit in VCX_CTL to */
			/* continue capture in non-continuous mode */
			VP_FSETH(vpCaptureHandle, VCASTAT, FRMC,VP_VCASTAT_FRMC_CLEAR);
			/* Clear CCMPA to enable next frame complete */
			/* interrupts */
			VP_FSETH(vpCaptureHandle, VPIS, CCMPA,VP_VPIS_CCMPA_CLEAR);
			capChaAFrameCount++; /* increment captured frame count */

			capNewFrame = 1;
		}
		if(vpis & _VP_VPIS_COVRA_MASK) /* overrun error */
		{
			capChaAOverrun++;
			VP_FSETH(vpCaptureHandle, VPIS, COVRA,VP_VPIS_COVRA_CLEAR);
		}
		if(vpis & _VP_VPIS_SERRA_MASK) /* synchronization error */
		{
			capChaASyncError++;
			VP_FSETH(vpCaptureHandle, VPIS, SERRA,VP_VPIS_SERRA_CLEAR);
		}
		if(vpis & _VP_VPIS_SFDA_MASK) /* short field detect */
		{
			capChaAShortFieldDetect++;
			VP_FSETH(vpCaptureHandle, VPIS, SFDA, VP_VPIS_SFDA_CLEAR);
		}
		if(vpis & _VP_VPIS_LFDA_MASK) /* long field detect */
		{
			capChaALongFieldDetect++;
			VP_FSETH(vpCaptureHandle, VPIS, LFDA, VP_VPIS_LFDA_CLEAR);
		}
		if(vpis & _VP_VPIS_VINTA1_MASK) /* long field detect */
		{
			capChaAField1Cnt++;
			VP_FSETH(vpCaptureHandle, VPIS, VINTA1, VP_VPIS_VINTA1_CLEAR);
		}
		if(vpis & _VP_VPIS_VINTA2_MASK) /* long field detect */
		{
			capChaAField2Cnt++;
			VP_FSETH(vpCaptureHandle, VPIS, VINTA2, VP_VPIS_VINTA2_CLEAR);
		}
		
}
/*---------------------------------------------------------------- */
/* Function : setupVPCapChaAEDMA */
/* Input(s) : portNumber, video port number i-e- 0, 1 or 2- */
/* Description : Sets up EDMA channels for Y, U, V events for */
/* channel A capture- */
/*---------------------------------------------------------------- */
void setupVPCapChaAEDMA(Int32 portNumber)
{
		Int32 YEvent, UEvent, VEvent;
		/* get channelA Y, U, V EDMA event numbers */
		switch(portNumber)
		{
			case VP_DEV0: YEvent = EDMA_CHA_VP0EVTYA;
			UEvent = EDMA_CHA_VP0EVTUA;
			VEvent = EDMA_CHA_VP0EVTVA;
			break;
			case VP_DEV1: YEvent = EDMA_CHA_VP1EVTYA;
			UEvent = EDMA_CHA_VP1EVTUA;
			VEvent = EDMA_CHA_VP1EVTVA;
			break;
			case VP_DEV2: YEvent = EDMA_CHA_VP2EVTYA;
			UEvent = EDMA_CHA_VP2EVTUA;
			VEvent = EDMA_CHA_VP2EVTVA;
			break;
		}
		/* Configure Y EDMA channel to move data from YSRCA */
		/* (FIFO) to Y-data buffer, capChaAYSpace */
		configVPCapEDMAChannel(&hEdmaVPCapChaAY, YEvent,
								&edmaCapChaAYTccNum,
								vpCaptureHandle->ysrcaAddr,
								(Uint32)capChaAYSpace,
								VCA_Y_EDMA_FRMCNT,
								VCA_Y_EDMA_ELECNT);
		/* Configure Cb EDMA channel to move data from CbSRCA */
		/* (FIFO) to Cb-data buffer, capChaACbSpace */
		configVPCapEDMAChannel(&hEdmaVPCapChaACb, UEvent,
								&edmaCapChaACbTccNum,
								vpCaptureHandle->cbsrcaAddr,
								(Uint32)capChaACbSpace,
								VCA_Y_EDMA_FRMCNT,
								VCA_Y_EDMA_ELECNT/2); /* (1/2) of Y-samples */
		/* Configure Cr EDMA channel to move data from CrSRCA */
		/* (FIFO) to Cr-data buffer, capChaACrSpace */
		configVPCapEDMAChannel(&hEdmaVPCapChaACr, VEvent,
								&edmaCapChaACrTccNum,
								vpCaptureHandle->crsrcaAddr,
								(Uint32)capChaACrSpace,
								VCA_Y_EDMA_FRMCNT,
								VCA_Y_EDMA_ELECNT/2); /* (1/2) of Y-samples */
		/* Enable three EDMA channels */
		EDMA_enableChannel(hEdmaVPCapChaAY);
		EDMA_enableChannel(hEdmaVPCapChaACb);
		EDMA_enableChannel(hEdmaVPCapChaACr);
}
/*---------------------------------------------------------------- */
/* Function : configVPCapEDMAChannel */
/* */
/* Input(s) : edmaHandle - pointer to EDMA handle- */
/* eventId - EDMA eventId- */
/* tccNum - pointer to transfer complete number- */
/* srcAddr - source address for EDMA transfer- */
/* dstAddr - destination address for EDMA transfer */
/* frameCount - frame count- */
/* elementCount - element count(32-bit element size)- */
/* */
/* Output(s): edmaHandle - edma Handle of the given event- */
/* tccNum - transfer complete code for the given */
/* event- */
/* */
/* Description : Configures the given VP capture EDMA channel- */
/* The source address update is fixed address mode */
/* because the captured data is read from the FIFO- */
/* In this example, the destination address mode is */
/* auto-increment- But, in real-time applications */
/* there is lot of flexibility in the way capture */
/* buffers can be managed like ping-pong and round */
/* robin,…etc- */
/*---------------------------------------------------------------- */
void configVPCapEDMAChannel(EDMA_Handle *edmaHandle, Int32 eventId,
									Int32 *tccNum, Uint32 srcAddr,
									Uint32 dstAddr, Uint32 frameCount,
									Uint32 elementCount)
{
		Int32 tcc = 0;
		/* Open Y EVT EDMA channel */
		*edmaHandle = EDMA_open(eventId, EDMA_OPEN_RESET);
		if(*edmaHandle == EDMA_HINV)
			while(1);
		/* allocate TCC for Y event */
		if((tcc = EDMA_intAlloc(-1)) == -1)
			while(1);
		/* Configure EDMA parameters */
		EDMA_configArgs(
				*edmaHandle,
				EDMA_OPT_RMK(
				EDMA_OPT_PRI_MEDIUM, /* medium priority */
				EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
				EDMA_OPT_2DS_NO, /* 1-dimensional source(FIFO) */
				EDMA_OPT_SUM_NONE, /* fixed src address mode(FIFO) */
				EDMA_OPT_2DD_YES, /* 2-dimensional destination */
				EDMA_OPT_DUM_INC, /* destination increment */
				EDMA_OPT_TCINT_YES, /* Enable transfer complete */
				/* indication */
				EDMA_OPT_TCC_OF(tcc & 0xF),
				EDMA_OPT_TCCM_OF(((tcc & 0x30) >> 4)),
				EDMA_OPT_ATCINT_NO, /* Disable Alternate Transfer */
				/* Complete Interrupt */
				EDMA_OPT_ATCC_OF(0),
				EDMA_OPT_PDTS_DISABLE, /* disable PDT(peripheral device */
				/* transfer) mode for source */
				EDMA_OPT_PDTD_DISABLE, /* disable PDT mode for dest */
				EDMA_OPT_LINK_NO, /* Disable linking */
				EDMA_OPT_FS_NO /* Array synchronization */
				),
				EDMA_SRC_RMK(srcAddr),
				EDMA_CNT_RMK(EDMA_CNT_FRMCNT_OF((frameCount - 1)),
				EDMA_CNT_ELECNT_OF(elementCount)),
				EDMA_DST_RMK(dstAddr),
				EDMA_IDX_RMK(EDMA_IDX_FRMIDX_OF((elementCount * 4)),
				EDMA_IDX_ELEIDX_OF(0)), /* note: 32-bit element size */
				/* no RLD in 2D and no linking */
				EDMA_RLD_RMK(EDMA_RLD_ELERLD_OF(0), EDMA_RLD_LINK_OF(0))
		);
		*tccNum = tcc;
}