davincihd_pll.h

用于dm6467 开发平台的uboot源码

/*
 *  Copyright 2007 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 */

/*
 *  PLL header file
 *
 */

#ifndef PLL_
#define PLL_

#ifdef __cplusplus
extern "C" {
#endif

#include "davincihd.h"

/* ------------------------------------------------------------------------ *
 *  PLL Clocking Mode                                                       *
 * ------------------------------------------------------------------------ */
#define CLKIN                   1
#define OSCIN                   0

/* ------------------------------------------------------------------------ *
 *  PLL Divide By                                                           *
 * ------------------------------------------------------------------------ */
#define DIV_1                   0
#define DIV_2                   1
#define DIV_3                   2
#define DIV_4                   3
#define DIV_5                   4
#define DIV_6                   5
#define DIV_7                   6
#define DIV_8                   7
#define DIV_9                   8
#define DIV_10                  9
#define DIV_11                  10
#define DIV_12                  11
#define DIV_13                  12
#define DIV_14                  13
#define DIV_15                  14
#define DIV_16                  15
#define DIV_17                  16
#define DIV_18                  17
#define DIV_19                  18
#define DIV_20                  19
#define DIV_21                  20
#define DIV_22                  21
#define DIV_23                  22
#define DIV_24                  23
#define DIV_25                  24
#define DIV_26                  25
#define DIV_27                  26
#define DIV_28                  27
#define DIV_29                  28
#define DIV_30                  29
#define DIV_31                  30
#define DIV_32                  31

/* ------------------------------------------------------------------------ *
 *  PLL0 Controller                                                         *
 * ------------------------------------------------------------------------ */
#define PLL0_BASE               0x01c40800
#define PLL0_PID                *( volatile Uint32* )( PLL0_BASE + 0x0 )
#define PLL0_RSTYPE             *( volatile Uint32* )( PLL0_BASE + 0xe4 )
#define PLL0_PLLCTL             *( volatile Uint32* )( PLL0_BASE + 0x100 )
#define PLL0_PLLM               *( volatile Uint32* )( PLL0_BASE + 0x110 )
#define PLL0_PLLDIV1            *( volatile Uint32* )( PLL0_BASE + 0x118 )
#define PLL0_PLLDIV2            *( volatile Uint32* )( PLL0_BASE + 0x11c )
#define PLL0_PLLDIV3            *( volatile Uint32* )( PLL0_BASE + 0x120 )
#define PLL0_POSTDIV            *( volatile Uint32* )( PLL0_BASE + 0x128 )
#define PLL0_BPDIV              *( volatile Uint32* )( PLL0_BASE + 0x12c )
#define PLL0_PLLCMD             *( volatile Uint32* )( PLL0_BASE + 0x138 )
#define PLL0_PLLSTAT            *( volatile Uint32* )( PLL0_BASE + 0x13c )
#define PLL0_ALNCTL             *( volatile Uint32* )( PLL0_BASE + 0x140 )
#define PLL0_DCHANGE            *( volatile Uint32* )( PLL0_BASE + 0x144 )
#define PLL0_CKEN               *( volatile Uint32* )( PLL0_BASE + 0x148 )
#define PLL0_CKSTAT             *( volatile Uint32* )( PLL0_BASE + 0x14c )
#define PLL0_SYSTAT             *( volatile Uint32* )( PLL0_BASE + 0x150 )
#define PLL0_PLLDIV4            *( volatile Uint32* )( PLL0_BASE + 0x160 )
#define PLL0_PLLDIV5            *( volatile Uint32* )( PLL0_BASE + 0x164 )
#define PLL0_PLLDIV6            *( volatile Uint32* )( PLL0_BASE + 0x168 )
#define PLL0_PLLDIV7            *( volatile Uint32* )( PLL0_BASE + 0x16c )
#define PLL0_PLLDIV8            *( volatile Uint32* )( PLL0_BASE + 0x170 )
#define PLL0_PLLDIV9            *( volatile Uint32* )( PLL0_BASE + 0x174 )

/* ------------------------------------------------------------------------ *
 *  PLL1 Controller                                                         *
 * ------------------------------------------------------------------------ */
#define PLL1_BASE               0x01c40c00
#define PLL1_PID                *( volatile Uint32* )( PLL1_BASE + 0x0 )
#define PLL1_PLLCTL             *( volatile Uint32* )( PLL1_BASE + 0x100 )
#define PLL1_PLLM               *( volatile Uint32* )( PLL1_BASE + 0x110 )
#define PLL1_PLLDIV1            *( volatile Uint32* )( PLL1_BASE + 0x118 )
#define PLL1_POSTDIV            *( volatile Uint32* )( PLL1_BASE + 0x128 )
#define PLL1_PLLCMD             *( volatile Uint32* )( PLL1_BASE + 0x138 )
#define PLL1_PLLSTAT            *( volatile Uint32* )( PLL1_BASE + 0x13c )
#define PLL1_ALNCTL             *( volatile Uint32* )( PLL1_BASE + 0x140 )
#define PLL1_DCHANGE            *( volatile Uint32* )( PLL1_BASE + 0x144 )
#define PLL1_CKEN               *( volatile Uint32* )( PLL1_BASE + 0x148 )
#define PLL1_CKSTAT             *( volatile Uint32* )( PLL1_BASE + 0x14c )
#define PLL1_SYSTAT             *( volatile Uint32* )( PLL1_BASE + 0x150 )

/* ------------------------------------------------------------------------ *
 *  Prototypes                                                              *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIHD_enablePll0( Uint16 clock_mode, Uint16 multiplier );
Int16 DAVINCIHD_enablePll1( Uint16 clock_mode, Uint16 multiplier, Uint16 ddr2_div );

Int16 DAVINCIHD_setPll0_divider( Uint16 pll_divider, Uint16 divide_by );

#ifdef __cplusplus
}
#endif

#endif