📄 davincihd.h
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/*
* Copyright 2007 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/
/*
* Definitions & Register
*
*/
#ifndef DAVINCIHD_
#define DAVINCIHD_
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------------------------------------------------------ *
* Variable types *
* ------------------------------------------------------------------------ */
#define Uint32 unsigned int
#define Uint16 unsigned short
#define Uint8 unsigned char
#define Int32 int
#define Int16 short
#define Int8 char
/* ------------------------------------------------------------------------ *
* Software Breakpoint code *
* Uses inline assembly command *
* ------------------------------------------------------------------------ */
#ifdef ARM_SIDE
#define SW_BREAKPOINT asm( " .long 0xe1200070" );
#elif DSP_SIDE
#define SW_BREAKPOINT asm( " .long 0x1001e000" );
#endif
/* ------------------------------------------------------------------------ *
* Device System Controller *
* ------------------------------------------------------------------------ */
#define SYS_BASE 0x01c40000
#define SYS_PINMUX0 *( volatile Uint32* )( SYS_BASE + 0x0 )
#define SYS_PINMUX1 *( volatile Uint32* )( SYS_BASE + 0x4 )
#define SYS_DSPBOOTADDR *( volatile Uint32* )( SYS_BASE + 0x8 )
#define SYS_SUSPSRC *( volatile Uint32* )( SYS_BASE + 0xc )
#define SYS_BOOTSTAT *( volatile Uint32* )( SYS_BASE + 0x10 )
#define SYS_BOOTCFG *( volatile Uint32* )( SYS_BASE + 0x14 )
#define SYS_SMTREFLEX *( volatile Uint32* )( SYS_BASE + 0x18 )
#define SYS_ARMBOOT *( volatile Uint32* )( SYS_BASE + 0x24 )
#define SYS_JTAG_ID *( volatile Uint32* )( SYS_BASE + 0x28 )
#define SYS_HDVICPBOOT *( volatile Uint32* )( SYS_BASE + 0x2c )
#define SYS_HPICTL *( volatile Uint32* )( SYS_BASE + 0x30 )
#define SYS_USBCTL *( volatile Uint32* )( SYS_BASE + 0x34 )
#define SYS_VIDCLKCTL *( volatile Uint32* )( SYS_BASE + 0x38 )
#define SYS_MSTPRI0 *( volatile Uint32* )( SYS_BASE + 0x3c )
#define SYS_MSTPRI1 *( volatile Uint32* )( SYS_BASE + 0x40 )
#define SYS_MSTPRI2 *( volatile Uint32* )( SYS_BASE + 0x44 )
#define SYS_VDD3P3VPWDN *( volatile Uint32* )( SYS_BASE + 0x48 )
#define SYS_TSIFCTL *( volatile Uint32* )( SYS_BASE + 0x50 )
#define SYS_PWMCTL *( volatile Uint32* )( SYS_BASE + 0x54 )
#define SYS_ETCCFG *( volatile Uint32* )( SYS_BASE + 0x58 )
#define SYS_CLKCTL *( volatile Uint32* )( SYS_BASE + 0x5c )
#define SYS_DSPINT *( volatile Uint32* )( SYS_BASE + 0x60 )
#define SYS_DSPINTSET *( volatile Uint32* )( SYS_BASE + 0x64 )
#define SYS_DSPINTCLR *( volatile Uint32* )( SYS_BASE + 0x68 )
#define SYS_VSCLKDIS *( volatile Uint32* )( SYS_BASE + 0x6c )
#define SYS_ARMINT *( volatile Uint32* )( SYS_BASE + 0x70 )
#define SYS_ARMINTSET *( volatile Uint32* )( SYS_BASE + 0x74 )
#define SYS_ARMINTCLR *( volatile Uint32* )( SYS_BASE + 0x78 )
#define SYS_ARMWAIT *( volatile Uint32* )( SYS_BASE + 0x7c )
/* ------------------------------------------------------------------------ *
* ARM Interrupt Controller *
* ------------------------------------------------------------------------ */
#ifdef ARM_SIDE
#define AINTC_BASE 0x01c48000
#define AINTC_FIQ0 *( volatile Uint32* )( AINTC_BASE + 0x0 )
#define AINTC_FIQ1 *( volatile Uint32* )( AINTC_BASE + 0x4 )
#define AINTC_IRQ0 *( volatile Uint32* )( AINTC_BASE + 0x8 )
#define AINTC_IRQ1 *( volatile Uint32* )( AINTC_BASE + 0xc )
#define AINTC_FIQENTRY *( volatile Uint32* )( AINTC_BASE + 0x10 )
#define AINTC_IRQENTRY *( volatile Uint32* )( AINTC_BASE + 0x14 )
#define AINTC_EINT0 *( volatile Uint32* )( AINTC_BASE + 0x18 )
#define AINTC_EINT1 *( volatile Uint32* )( AINTC_BASE + 0x1c )
#define AINTC_INCTL *( volatile Uint32* )( AINTC_BASE + 0x20 )
#define AINTC_EABASE *( volatile Uint32* )( AINTC_BASE + 0x24 )
#define AINTC_INTPRI0 *( volatile Uint32* )( AINTC_BASE + 0x30 )
#define AINTC_INTPRI1 *( volatile Uint32* )( AINTC_BASE + 0x34 )
#define AINTC_INTPRI2 *( volatile Uint32* )( AINTC_BASE + 0x38 )
#define AINTC_INTPRI3 *( volatile Uint32* )( AINTC_BASE + 0x3c )
#define AINTC_INTPRI4 *( volatile Uint32* )( AINTC_BASE + 0x40 )
#define AINTC_INTPRI5 *( volatile Uint32* )( AINTC_BASE + 0x44 )
#define AINTC_INTPRI6 *( volatile Uint32* )( AINTC_BASE + 0x48 )
#define AINTC_INTPRI7 *( volatile Uint32* )( AINTC_BASE + 0x4c )
#endif
/* ------------------------------------------------------------------------ *
* DSP CACHE Controller *
* ------------------------------------------------------------------------ */
#ifdef DSP_SIDE
#define CACHE_BASE 0x01840000
#define CACHE_L2CFG *( volatile Uint32* )( CACHE_BASE + 0x0000 )
#define CACHE_L1PCFG *( volatile Uint32* )( CACHE_BASE + 0x0020 )
#define CACHE_L1PCC *( volatile Uint32* )( CACHE_BASE + 0x0024 )
#define CACHE_L1DCFG *( volatile Uint32* )( CACHE_BASE + 0x0040 )
#define CACHE_L1DCC *( volatile Uint32* )( CACHE_BASE + 0x0044 )
#define CACHE_EDMAWEIGHT *( volatile Uint32* )( CACHE_BASE + 0x1000 )
#define CACHE_L2ALLOC0 *( volatile Uint32* )( CACHE_BASE + 0x2000 )
#define CACHE_L2ALLOC1 *( volatile Uint32* )( CACHE_BASE + 0x2004 )
#define CACHE_L2ALLOC2 *( volatile Uint32* )( CACHE_BASE + 0x2008 )
#define CACHE_L2ALLOC3 *( volatile Uint32* )( CACHE_BASE + 0x200c )
#define CACHE_L2WBAR *( volatile Uint32* )( CACHE_BASE + 0x4000 )
#define CACHE_L2WWC *( volatile Uint32* )( CACHE_BASE + 0x4004 )
#define CACHE_L2WIBAR *( volatile Uint32* )( CACHE_BASE + 0x4010 )
#define CACHE_L2WIWC *( volatile Uint32* )( CACHE_BASE + 0x4014 )
#define CACHE_L2IBAR *( volatile Uint32* )( CACHE_BASE + 0x4018 )
#define CACHE_L2IWC *( volatile Uint32* )( CACHE_BASE + 0x401c )
#define CACHE_L1PIBAR *( volatile Uint32* )( CACHE_BASE + 0x4020 )
#define CACHE_L1PIWC *( volatile Uint32* )( CACHE_BASE + 0x4024 )
#define CACHE_L1DWIBAR *( volatile Uint32* )( CACHE_BASE + 0x4030 )
#define CACHE_L1DWIWC *( volatile Uint32* )( CACHE_BASE + 0x4034 )
#define CACHE_L1DWBAR *( volatile Uint32* )( CACHE_BASE + 0x4040 )
#define CACHE_L1DWWC *( volatile Uint32* )( CACHE_BASE + 0x4044 )
#define CACHE_L1DIBAR *( volatile Uint32* )( CACHE_BASE + 0x4048 )
#define CACHE_L1DIWC *( volatile Uint32* )( CACHE_BASE + 0x404c )
#define CACHE_L2WB *( volatile Uint32* )( CACHE_BASE + 0x5000 )
#define CACHE_L2WBINV *( volatile Uint32* )( CACHE_BASE + 0x5004 )
#define CACHE_L2INV *( volatile Uint32* )( CACHE_BASE + 0x5008 )
#define CACHE_L1PINV *( volatile Uint32* )( CACHE_BASE + 0x5028 )
#define CACHE_L1DWB *( volatile Uint32* )( CACHE_BASE + 0x5040 )
#define CACHE_L1DWBINV *( volatile Uint32* )( CACHE_BASE + 0x5044 )
#define CACHE_L1DINV *( volatile Uint32* )( CACHE_BASE + 0x5048 )
#define CACHE_MAR_BASE ( CACHE_BASE + 0x8000 )
#endif
/* ------------------------------------------------------------------------ *
* DSP Interrupt Controller *
* ------------------------------------------------------------------------ */
#ifdef DSP_SIDE
#define DINTC_BASE 0x01800000
#define DINTC_EVTFLAG0 *( volatile Uint32* )( DINTC_BASE + 0x0 )
#define DINTC_EVTFLAG1 *( volatile Uint32* )( DINTC_BASE + 0x4 )
#define DINTC_EVTFLAG2 *( volatile Uint32* )( DINTC_BASE + 0x8 )
#define DINTC_EVTFLAG3 *( volatile Uint32* )( DINTC_BASE + 0xc )
#define DINTC_EVTSET0 *( volatile Uint32* )( DINTC_BASE + 0x20 )
#define DINTC_EVTSET1 *( volatile Uint32* )( DINTC_BASE + 0x24 )
#define DINTC_EVTSET2 *( volatile Uint32* )( DINTC_BASE + 0x28 )
#define DINTC_EVTSET3 *( volatile Uint32* )( DINTC_BASE + 0x2c )
#define DINTC_EVTCLR0 *( volatile Uint32* )( DINTC_BASE + 0x40 )
#define DINTC_EVTCLR1 *( volatile Uint32* )( DINTC_BASE + 0x44 )
#define DINTC_EVTCLR2 *( volatile Uint32* )( DINTC_BASE + 0x48 )
#define DINTC_EVTCLR3 *( volatile Uint32* )( DINTC_BASE + 0x4c )
#define DINTC_EVTMASK0 *( volatile Uint32* )( DINTC_BASE + 0x80 )
#define DINTC_EVTMASK1 *( volatile Uint32* )( DINTC_BASE + 0x84 )
#define DINTC_EVTMASK2 *( volatile Uint32* )( DINTC_BASE + 0x88 )
#define DINTC_EVTMASK3 *( volatile Uint32* )( DINTC_BASE + 0x8c )
#define DINTC_MEVTFLAG0 *( volatile Uint32* )( DINTC_BASE + 0xa0 )
#define DINTC_MEVTFLAG1 *( volatile Uint32* )( DINTC_BASE + 0xa4 )
#define DINTC_MEVTFLAG2 *( volatile Uint32* )( DINTC_BASE + 0xa8 )
#define DINTC_MEVTFLAG3 *( volatile Uint32* )( DINTC_BASE + 0xac )
#define DINTC_EXPMASK0 *( volatile Uint32* )( DINTC_BASE + 0xc0 )
#define DINTC_EXPMASK1 *( volatile Uint32* )( DINTC_BASE + 0xc4 )
#define DINTC_EXPMASK2 *( volatile Uint32* )( DINTC_BASE + 0xc8 )
#define DINTC_EXPMASK3 *( volatile Uint32* )( DINTC_BASE + 0xcc )
#define DINTC_MEXPFLAG0 *( volatile Uint32* )( DINTC_BASE + 0xe0 )
#define DINTC_MEXPFLAG1 *( volatile Uint32* )( DINTC_BASE + 0xe4 )
#define DINTC_MEXPFLAG2 *( volatile Uint32* )( DINTC_BASE + 0xe8 )
#define DINTC_MEXPFLAG3 *( volatile Uint32* )( DINTC_BASE + 0xec )
#define DINTC_INTMUX1 *( volatile Uint32* )( DINTC_BASE + 0x104 )
#define DINTC_INTMUX2 *( volatile Uint32* )( DINTC_BASE + 0x108 )
#define DINTC_INTMUX3 *( volatile Uint32* )( DINTC_BASE + 0x10c )
#define DINTC_AEGMUX0 *( volatile Uint32* )( DINTC_BASE + 0x140 )
#define DINTC_AEGMUX1 *( volatile Uint32* )( DINTC_BASE + 0x144 )
#define DINTC_INTXSTAT *( volatile Uint32* )( DINTC_BASE + 0x180 )
#define DINTC_INTXCLR *( volatile Uint32* )( DINTC_BASE + 0x184 )
#define DINTC_INTDMASK *( volatile Uint32* )( DINTC_BASE + 0x188 )
#define DINTC_EVTASRT *( volatile Uint32* )( DINTC_BASE + 0x1c0 )
#endif
/* ------------------------------------------------------------------------ *
* EMIFA Controller *
* ------------------------------------------------------------------------ */
#define EMIFA_BASE 0x20008000
#define EMIFA_AWCCR *( volatile Uint32* )( EMIFA_BASE + 0x4 )
#define EMIFA_A1CR *( volatile Uint32* )( EMIFA_BASE + 0x10 )
#define EMIFA_A2CR *( volatile Uint32* )( EMIFA_BASE + 0x14 )
#define EMIFA_A3CR *( volatile Uint32* )( EMIFA_BASE + 0x18 )
#define EMIFA_A4CR *( volatile Uint32* )( EMIFA_BASE + 0x1c )
#define EMIFA_EIRR *( volatile Uint32* )( EMIFA_BASE + 0x40 )
#define EMIFA_EIMR *( volatile Uint32* )( EMIFA_BASE + 0x44 )
#define EMIFA_EIMSR *( volatile Uint32* )( EMIFA_BASE + 0x48 )
#define EMIFA_EIMCR *( volatile Uint32* )( EMIFA_BASE + 0x4c )
#define EMIFA_NANDFCR *( volatile Uint32* )( EMIFA_BASE + 0x60 )
#define EMIFA_NANDFSR *( volatile Uint32* )( EMIFA_BASE + 0x64 )
#define EMIFA_NANDF1ECC *( volatile Uint32* )( EMIFA_BASE + 0x70 )
#define EMIFA_NANDF2ECC *( volatile Uint32* )( EMIFA_BASE + 0x74 )
#define EMIFA_NANDF3ECC *( volatile Uint32* )( EMIFA_BASE + 0x78 )
#define EMIFA_NANDF4ECC *( volatile Uint32* )( EMIFA_BASE + 0x7c )
#define EMIFA_MAX_TIMEOUT 0x3ffffffc
#define EMIFA_MAX_TIMEOUT_8BIT 0x3ffffffc
#define EMIFA_MAX_TIMEOUT_16BIT 0x3ffffffd
#define EMIF_CS2 2
#define EMIF_CS3 3
#define EMIF_CS4 4
#define EMIF_CS5 5
#define EMIF_CS2_BASE 0x42000000
#define EMIF_CS3_BASE 0x44000000
#define EMIF_CS4_BASE 0x46000000
#define EMIF_CS5_BASE 0x48000000
#define EMIF_MODE 1
#define NAND_MODE 0
/* ------------------------------------------------------------------------ *
* HDVICP0 Controller *
* ------------------------------------------------------------------------ */
#define HDVICP0_C64X 0x11400000
#define HDVICP0_RW_PORT 0x40400000
#define HDVICP0_R_PORT 0x40440000
#define HDVICP0_W_PORT 0x40480000
#define HDVICP0_BASE 0x02000000
/* ------------------------------------------------------------------------ *
* HDVICP1 Controller *
* ------------------------------------------------------------------------ */
#define HDVICP1_C64X 0x11600000
#define HDVICP1_RW_PORT 0x40600000
#define HDVICP1_R_PORT 0x40640000
#define HDVICP1_W_PORT 0x40680000
#define HDVICP1_BASE 0x02200000
/* ------------------------------------------------------------------------ *
* Function Renaming *
* ------------------------------------------------------------------------ */
#define _wait DAVINCIHD_wait
#define _waitusec DAVINCIHD_waitusec
#define _waitmsec DAVINCIHD_waitmsec
/* ------------------------------------------------------------------------ *
* Prototypes *
* ------------------------------------------------------------------------ */
/* Board Initialization */
Int16 DAVINCIHD_init( );
/* Wait Functions */
void DAVINCIHD_wait ( Uint32 delay );
void DAVINCIHD_waitusec( Uint32 usec );
void DAVINCIHD_waitmsec( Uint32 msec );
/* Pin Mux Functions */
Int16 DAVINCIHD_setupPinMux( );
Int16 DAVINCIHD_setPinMux( Uint32 pinmux0, Uint32 pinmux1, Uint32 vdd3p3vpwdn );
Int16 DAVINCIHD_clrPinMux( Uint32 pinmux0, Uint32 pinmux1, Uint32 vdd3p3vpwdn );
/* EMIF Funtions */
Int16 DAVINCIHD_resetEMIF( Uint16 chip_select );
Int16 DAVINCIHD_setupEMIF( Uint16 chip_select, Uint32 timings, Uint16 emif_mode );
#ifdef __cplusplus
}
#endif
#endif
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