📄 davincihd_ddr.c
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/*
* Copyright 2007 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/
/*
* DDR Setup
*
*/
#include "davincihd_ddr.h"
#include "davincihd_psc.h"
/* ------------------------------------------------------------------------ *
* *
* DAVINCIHD_DDR_init( freq ) *
* Setup the DDR2 & DDR2 PHY to 300 MHz *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIHD_DDR_init( Int32 freq )
{
Uint32 davincihd_ddr_init_fn;
Uint32 refresh_rate;
static Uint32 dummy_read;
/*
* Check 0 - Check to see if we are running from DDR
* If so, then its a bad idea to run this DDR setup
*/
davincihd_ddr_init_fn = ( Uint32 )&DAVINCIHD_DDR_init;
if ( ( davincihd_ddr_init_fn >= ( DDR_BASE ) )
&& ( davincihd_ddr_init_fn <= ( DDR_BASE + DDR_SIZE ) ) )
return -1;
/*
* Step 0 - Stop all DDR accesses.
*/
/*
* Step 1 - Setup PLL2
* Step 2 - Enable DDR2 PHY
*/
DAVINCIHD_PSC_changeState( LPSC_DDR2_EMIF, PSC_ENABLE );
/*
* Step 3 - DDR2 Initialization
*/
DDR_DDRPHYCR = 0 // DDR PHY Control Register
| ( 0x1400190 << 6 ) // Magic number
| ( 0 << 5 ) // DLL release
| ( 0 << 4 ) // DLL powered up
| ( 5 << 0 ); // Read latency ( CAS + RT - 1 )
DDR_SDBCR = 0 // DDR Bank Config
| ( 0 << 23 ) // Boot unlock = No
| ( 2 << 19 ) // Reserved = ( 2 )
| ( 0 << 18 ) // Drive Strength= Normal
| ( 3 << 16 ) // Reserved = ( 3 )
| ( 1 << 15 ) // Modify SDBCR = Yes
| ( 0 << 14 ) // Bus width = 32-bit
| ( 5 << 9 ) // CAS latency = 5
| ( 3 << 4 ) // Bank Setup = 8 banks
| ( 2 << 0 ); // Page Size = 1024-word / 10 column bits
switch ( freq )
{
/* Timing set for 297 MHz */
case 297:
DDR_SDTIMR = 0 // DDR Timing Register
| ( 37 << 25 ) // tRFC = ( 127.5 ns / 3.33 ns ) - 1
| ( 4 << 22 ) // tRP = ( 15 ns / 3.33 ns ) - 1
| ( 4 << 19 ) // tRCD = ( 15 ns / 3.33 ns ) - 1
| ( 4 << 16 ) // tWR = ( 15 ns / 3.33 ns ) - 1
| ( 11 << 11 ) // tRAS = ( 40 ns / 3.33 ns ) - 1
| ( 16 << 6 ) // tRC = ( 55 ns / 3.33 ns ) - 1
| ( 2 << 3 ) // tRRD = ( 10 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tWTR = ( 7.5 ns / 3.33 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 40 << 16 ) // tXSNR= ( 137.5 ns / 3.33 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 2 << 5 ) // tRTP = ( 7.5 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1*/
refresh_rate = 2317; // 7.8 * 297
break;
/* Timing set for 283.5 MHz */
case 283:
DDR_SDTIMR = 0 // DDR Timing Register
| ( 36 << 25 ) // tRFC = ( 127.5 ns / 3.33 ns ) - 1
| ( 4 << 22 ) // tRP = ( 15 ns / 3.33 ns ) - 1
| ( 4 << 19 ) // tRCD = ( 15 ns / 3.33 ns ) - 1
| ( 4 << 16 ) // tWR = ( 15 ns / 3.33 ns ) - 1
| ( 11 << 11 ) // tRAS = ( 40 ns / 3.33 ns ) - 1
| ( 15 << 6 ) // tRC = ( 55 ns / 3.33 ns ) - 1
| ( 2 << 3 ) // tRRD = ( 10 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tWTR = ( 7.5 ns / 3.33 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 38 << 16 ) // tXSNR= ( 137.5 ns / 3.33 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 2 << 5 ) // tRTP = ( 7.5 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1*/
refresh_rate = 2212; // 7.8 * 283.5
break;
/* Timing set for 270 MHz */
case 270:
DDR_SDTIMR = 0 // DDR Timing Register
| ( 34 << 25 ) // tRFC = ( 127.5 ns / 3.33 ns ) - 1
| ( 4 << 22 ) // tRP = ( 15 ns / 3.33 ns ) - 1
| ( 4 << 19 ) // tRCD = ( 15 ns / 3.33 ns ) - 1
| ( 4 << 16 ) // tWR = ( 15 ns / 3.33 ns ) - 1
| ( 10 << 11 ) // tRAS = ( 40 ns / 3.33 ns ) - 1
| ( 14 << 6 ) // tRC = ( 55 ns / 3.33 ns ) - 1
| ( 2 << 3 ) // tRRD = ( 10 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tWTR = ( 7.5 ns / 3.33 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 37 << 16 ) // tXSNR= ( 137.5 ns / 3.33 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 2 << 5 ) // tRTP = ( 7.5 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1*/
refresh_rate = 2106; // 7.8 * 270
break;
/* Timing set for 216.5 MHz */
case 256:
DDR_SDTIMR = 0 // DDR Timing Register
| ( 32 << 25 ) // tRFC = ( 127.5 ns / 3.33 ns ) - 1
| ( 3 << 22 ) // tRP = ( 15 ns / 3.33 ns ) - 1
| ( 3 << 19 ) // tRCD = ( 15 ns / 3.33 ns ) - 1
| ( 3 << 16 ) // tWR = ( 15 ns / 3.33 ns ) - 1
| ( 10<< 11 ) // tRAS = ( 40 ns / 3.33 ns ) - 1
| ( 14<< 6 ) // tRC = ( 55 ns / 3.33 ns ) - 1
| ( 2 << 3 ) // tRRD = ( 10 ns / 3.33 ns ) - 1
| ( 1 << 0 ); // tWTR = ( 7.5 ns / 3.33 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 35 << 16 ) // tXSNR= ( 137.5 ns / 3.33 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 1 << 5 ) // tRTP = ( 7.5 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1
refresh_rate = 2001; // 7.8 * 256
break;
/* Timing set for 216 MHz */
case 216:
DDR_SDTIMR = 0 // DDR Timing Register
| ( 27 << 25 ) // tRFC = ( 127.5 ns / 3.33 ns ) - 1
| ( 3 << 22 ) // tRP = ( 15 ns / 3.33 ns ) - 1
| ( 3 << 19 ) // tRCD = ( 15 ns / 3.33 ns ) - 1
| ( 3 << 16 ) // tWR = ( 15 ns / 3.33 ns ) - 1
| ( 8 << 11 ) // tRAS = ( 40 ns / 3.33 ns ) - 1
| ( 11<< 6 ) // tRC = ( 55 ns / 3.33 ns ) - 1
| ( 2 << 3 ) // tRRD = ( 10 ns / 3.33 ns ) - 1
| ( 1 << 0 ); // tWTR = ( 7.5 ns / 3.33 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 29 << 16 ) // tXSNR= ( 137.5 ns / 3.33 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 1 << 5 ) // tRTP = ( 7.5 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1
refresh_rate = 1685; // 7.8 * 216
break;
/* Timing set for 148.5 MHz */
case 148:
DDR_SDTIMR = 0 // DDR Timing Register
| ( 18 << 25 ) // tRFC = ( 127.5 ns / 3.33 ns ) - 1
| ( 2 << 22 ) // tRP = ( 15 ns / 3.33 ns ) - 1
| ( 2 << 19 ) // tRCD = ( 15 ns / 3.33 ns ) - 1
| ( 2 << 16 ) // tWR = ( 15 ns / 3.33 ns ) - 1
| ( 5 << 11 ) // tRAS = ( 40 ns / 3.33 ns ) - 1
| ( 8 << 6 ) // tRC = ( 55 ns / 3.33 ns ) - 1
| ( 1 << 3 ) // tRRD = ( 10 ns / 3.33 ns ) - 1
| ( 1 << 0 ); // tWTR = ( 7.5 ns / 3.33 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 20 << 16 ) // tXSNR= ( 137.5 ns / 3.33 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 1 << 5 ) // tRTP = ( 7.5 ns / 3.33 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1
refresh_rate = 1159; // 7.8 * 216
break;
}
//refresh_rate = ( 7.8 * freq );
DDR_SDBCR &= ~0x00008000; // SDBCR cannot be modified
DDR_SDRCR = 0
| ( 0 << 31 ) // Exits self-refresh
| ( 0 << 30 ) // Disable MCLK stopping
| refresh_rate; // Refresh Control = 7.8 usec * freq
/*
* Step 4 - Dummy Read
*/
dummy_read = DDR_BASE;
dummy_read = *( volatile Uint32* )dummy_read;
/*
* Step 5 - Soft Reset ( SYNCRESET followed by ENABLE ) of DDR2 PHY
*/
DAVINCIHD_PSC_changeState( LPSC_DDR2_EMIF, PSC_SYNCRESET );
DAVINCIHD_PSC_changeState( LPSC_DDR2_EMIF, PSC_ENABLE );
return 0;
}
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