davincihd.c

用于dm6467 开发平台的uboot源码

        | ( 0 << 8 )        // TSIF1 Output Clock [CRG1_VCXI]
        | ( 0 << 4 )        // TSIF0 Clock Source [CRG0_VCXI]
        | ( 0 << 0 );       // TSIF0 Output Clock [CRG0_VCXI]

    /* VS Clock Disable */
    SYS_VSCLKDIS = 0
        | ( 1 << 11 )       // VPIF Ch 3    [Disable]
        | ( 1 << 10 )       // VPIF Ch 2    [Disable]
        | ( 1 << 9 )        // VPIF Ch 1    [Disable]
        | ( 1 << 8 )        // VPIF Ch 0    [Disable]
        | ( 1 << 7 )        // TSIF1 Count  [Disable]
        | ( 1 << 6 )        // TSIF0 Count  [Disable]
        | ( 1 << 5 )        // TSIF1 TX Clk [Disable]
        | ( 1 << 4 )        // TSIF0 TX Clk [Disable]
        | ( 1 << 3 )        // TSIF1 RX Clk [Disable]
        | ( 1 << 2 )        // TSIF0 RX Clk [Disable]
        | ( 1 << 1 )        // CRG 1 Enable [Disable]
        | ( 1 << 0 );       // CRG 0 Enable [Disable]

    return 0;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _setPinMux( pinmux0, pinmux1 )                                          *
 *      Set pin mux depending on the value of ( pinmux0 ) & ( pinmux1 )     *
 *      The 1's bit indicates which field to enable.                        *
 *                                                                          *
 *      Inputs:                                                             *
 *              pinmux0     -> PinMux Reg 0                                 *
 *              pinmux1     -> PinMux Reg 1                                 *
 *              vdd3p3vpwdn -> 3.3V power down register                     *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIHD_setPinMux( Uint32 pinmux0, Uint32 pinmux1, Uint32 vdd3p3vpwdn )
{
    SYS_PINMUX0     |= pinmux0;
    SYS_PINMUX1     |= pinmux1;
    SYS_VDD3P3VPWDN |= vdd3p3vpwdn;
    return 0;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _clrPinMux( pinmux0, pinmux1 )                                          *
 *      Clear pin mux depending on the value of ( pinmux0 ) & ( pinmux1 )   *
 *      The 1's bit indicates which field to enable.                        *
 *                                                                          *
 *      Inputs:                                                             *
 *              pinmux0     -> PinMux Reg 0                                 *
 *              pinmux1     -> PinMux Reg 1                                 *
 *              vdd3p3vpwdn -> 3.3V power down register                     *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIHD_clrPinMux( Uint32 pinmux0, Uint32 pinmux1, Uint32 vdd3p3vpwdn )
{
    SYS_PINMUX0     &= ~pinmux0;
    SYS_PINMUX1     &= ~pinmux1;
    SYS_VDD3P3VPWDN &= ~vdd3p3vpwdn;
    return 0;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _resetEMIF( chip_select )                                               *
 *      Reset EMIFA chip select timings to MAX                              *
 *                                                                          *
 *      Inputs:                                                             *
 *              chip_select -> EMIF_CS2/3/4/5                               *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIHD_resetEMIF( Uint16 chip_select )
{
    switch ( chip_select )
    {
        case EMIF_CS2:
            EMIFA_A1CR |= EMIFA_MAX_TIMEOUT;    // CS2
            EMIFA_NANDFCR &= ~( 1 << 0 );       // NAND Flash [OFF]
            break;
        case EMIF_CS3:
            EMIFA_A2CR |= EMIFA_MAX_TIMEOUT;    // CS3
            EMIFA_NANDFCR &= ~( 1 << 1 );       // NAND Flash [OFF]
            break;
        case EMIF_CS4:
            EMIFA_A3CR |= EMIFA_MAX_TIMEOUT;    // CS4
            EMIFA_NANDFCR &= ~( 1 << 2 );       // NAND Flash [OFF]
            break;
        case EMIF_CS5:
            EMIFA_A4CR |= EMIFA_MAX_TIMEOUT;    // CS5
            EMIFA_NANDFCR &= ~( 1 << 3 );       // NAND Flash [OFF]
            break;
        default:
            return -1;
    }
    return 0;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _setupEMIF( chip_select, emif_timing, emif_mode  )                      *
 *      Set EMIFA chip select timings                                       *
 *                                                                          *
 *      Inputs:                                                             *
 *              chip_select -> EMIF_CS2/3/4/5                               *
 *              timing      -> Timing                                       *
 *              emif_mode   -> NAND_MODE or EMIF_MODE                       *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIHD_setupEMIF( Uint16 chip_select, Uint32 timing, Uint16 emif_mode )
{
    Uint32 nand_enable_bit;

    switch ( chip_select )
    {
        case EMIF_CS2:
            EMIFA_A1CR = timing;                // CS2
            break;
        case EMIF_CS3:
            EMIFA_A2CR = timing;                // CS3
            break;
        case EMIF_CS4:
            EMIFA_A3CR = timing;                // CS4
            break;
        case EMIF_CS5:
            EMIFA_A4CR = timing;                // CS5
            break;
        default:
            return -1;
    }

    nand_enable_bit = 1 << ( chip_select - EMIF_CS2 );

    switch( emif_mode )
    {
        case NAND_MODE:
            EMIFA_NANDFCR |= nand_enable_bit;   // NAND Flash [ON]
            break;

        case EMIF_MODE:
            EMIFA_NANDFCR &= ~nand_enable_bit;  // NAND Flash [OFF]
            break;
    }

    return 0;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _wait( delay )                                                          *
 *      Wait in a software loop for 'x' delay                               *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void DAVINCIHD_wait( Uint32 delay )
{
    volatile Uint32 i;
    for ( i = 0 ; i < delay ; i++ ){ };
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _waitusec( usec )                                                       *
 *      Wait in a software loop for 'x' microseconds                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void DAVINCIHD_waitusec( Uint32 usec )
{
    #ifdef ARM_SIDE
        DAVINCIHD_wait( usec * 2 );
    #elif DSP_SIDE
        DAVINCIHD_wait( usec * 28 );
    #endif
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  _waitmsec( msec )                                                       *
 *      Wait in a software loop for 'x' milliseconds                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void DAVINCIHD_waitmsec( Uint32 msec )
{
    _waitusec( 1000 * msec );
}