📄 davincihd_arm.gel
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else
*pll_ctl |= 0x0100; // External Clock
/*
* Step 2 - Set PLL to bypass
* - Wait for PLL to stabilize
*/
*pll_ctl &= ~0x0021;
_wait( 150 );
/*
* Step 3 - Reset PLL
*/
*pll_ctl |= 0x0008;
/*
* Step 4 - Disable PLL
* Step 5 - Powerup PLL
* Step 6 - Enable PLL
* Step 7 - Wait for PLL to stabilize
*/
*pll_ctl |= 0x0010; // Disable PLL
*pll_ctl &= ~0x0002; // Power up PLL
*pll_ctl &= ~0x0010; // Enable PLL
_wait( 150 ); // Wait for PLL to stabilize
/*
* Step 8 - Load PLL multiplier
*/
*pll_pllm = pll_mult & 0x3f;
/*
* Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio )
* 1:DDR2
*/
*pll_bpdiv = 0x8000 | bypass_div;
*pll_div2 = 0x8000 | ( ddr2_div & 0x1f );
*pll_cmd |= 0x0001; // Set phase alignment
while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment
/*
* Step 10 - Wait for PLL to reset ( 2000 cycles )
* Step 11 - Release from reset
*/
_wait( 2000 );
*pll_ctl &= ~0x0008;
/*
* Step 12 - Wait for PLL to re-lock ( 2000 cycles )
* Step 13 - Switch out of BYPASS mode
*/
_wait( 2000 );
*pll_ctl |= 0x0001;
pll1_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 );
ddr2_freq = pll1_freq / ( 2 * ( ( *pll_div2 & 0x1f ) + 1 ) );
GEL_TextOut( "(DDR2 Phy = %d MHz + ",,,,, ddr2_freq );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Done]\n" );
}
/* ------------------------------------------------------------------------ *
* *
* setup_ddr2( ) *
* Configure DDR2 to run at specified frequency. *
* *
* ------------------------------------------------------------------------ */
setup_ddr2( int freq )
{
#define DDR_SDBCR *( unsigned int* )( 0x20000008 )
#define DDR_SDRCR *( unsigned int* )( 0x2000000c )
#define DDR_SDTIMR *( unsigned int* )( 0x20000010 )
#define DDR_SDTIMR2 *( unsigned int* )( 0x20000014 )
#define DDR_DDRPHYCR *( unsigned int* )( 0x200000e4 )
int dummy_read;
int pch_nch;
int refresh_rate;
GEL_TextOut( "Setup DDR2 (%d MHz + 32-bit bus)... ",,,,, freq );
/*
* Step 1 - Setup pll1
* Step 2 - Enable DDR2 PHY
*/
psc_change_state( 20, 3 );
/*
* Step 3 - DDR2 Initialization
*/
DDR_DDRPHYCR = 0x50006406; // DLL powered, ReadLatency=6
DDR_SDBCR = 0x00138a32; // DDR Bank: 32-bit bus, CAS=5,
// 8 banks, 1024-word pg
if ( freq == 297 )
{
DDR_SDTIMR = 0 // DDR Timing Register
| ( 37 << 25 ) // tRFC = ( 127.5 ns / 3.37 ns ) - 1
| ( 4 << 22 ) // tRP = ( 15 ns / 3.37 ns ) - 1
| ( 4 << 19 ) // tRCD = ( 15 ns / 3.37 ns ) - 1
| ( 4 << 16 ) // tWR = ( 15 ns / 3.37 ns ) - 1
| ( 11 << 11 ) // tRAS = ( 40 ns / 3.37 ns ) - 1
| ( 16 << 6 ) // tRC = ( 55 ns / 3.37 ns ) - 1
| ( 2 << 3 ) // tRRD = ( 10 ns / 3.37 ns ) - 1
| ( 2 << 0 ); // tWTR = ( 7.5 ns / 3.37 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 40 << 16 ) // tXSNR= ( 137.5 ns / 3.37 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 cycles ) - 1
| ( 2 << 5 ) // tRTP = ( 7.5 ns / 3.37 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 cycles ) - 1*/
refresh_rate = 2317; // 7.8 us * 297 MHz
}
DDR_SDBCR = 0x00130a32; // DDR Bank: cannot modify
DDR_SDRCR = refresh_rate; // Refresh Control [ 7.8 usec * freq ]
/*
* Step 4 - Dummy Read from DDR2
*/
dummy_read = *( int* )0x80000000;
/*
* Step 5 - Soft Reset ( SYNCRESET followed by ENABLE ) of DDR2 PHY
*/
psc_change_state( 20, 1 );
psc_change_state( 20, 3 );
GEL_TextOut( "[Done]\n" );
}
hotmenu
Setup_DDR_297_MHz( )
{
setup_pll_1( 0, 21, 0 ); // [DDR @ 297 MHz] w/ Onchip Oscillator
setup_ddr2( 297 );
}
/* ------------------------------------------------------------------------ *
* *
* setup_aemif( ) *
* Setup Async-EMIF to Max Wait cycles and specified bus width. *
* *
* ------------------------------------------------------------------------ */
#define EMIF_CS2 2
#define EMIF_CS3 3
#define EMIF_CS4 4
#define EMIF_CS5 5
#define NO_NAND_FLASH 0
#define YES_NAND_FLASH 1
setup_aemif( int chip_select, int chip_config, int using_nand_flash )
{
int nand_flash_bit;
#define AEMIF_A1CR *( unsigned int* )( 0x20008010 )
#define AEMIF_A2CR *( unsigned int* )( 0x20008014 )
#define AEMIF_A3CR *( unsigned int* )( 0x20008018 )
#define AEMIF_A4CR *( unsigned int* )( 0x2000801C )
#define AEMIF_NANDFCR *( unsigned int* )( 0x20008060 )
/* Setup AEMIF memory space */
if ( chip_select == EMIF_CS2 )
AEMIF_A1CR = chip_config;
else if ( chip_select == EMIF_CS3 )
AEMIF_A2CR = chip_config;
else if ( chip_select == EMIF_CS4 )
AEMIF_A3CR = chip_config;
else if ( chip_select == EMIF_CS5 )
AEMIF_A4CR = chip_config;
else
return;
nand_flash_bit = 1 << ( chip_config - 2 );
/* Enable or Disable Hw NAND controller */
if ( using_nand_flash == NO_NAND_FLASH )
AEMIF_NANDFCR &= ~nand_flash_bit;
else
AEMIF_NANDFCR |= nand_flash_bit;
}
/*hotmenu*/
Reset_EMIF_8Bit_Bus( )
{
int max_timeout = 0x3ffffffc;
setup_aemif( EMIF_CS2, max_timeout, NO_NAND_FLASH );
setup_aemif( EMIF_CS3, max_timeout, NO_NAND_FLASH );
setup_aemif( EMIF_CS4, max_timeout, NO_NAND_FLASH );
setup_aemif( EMIF_CS5, max_timeout, NO_NAND_FLASH );
}
/* ------------------------------------------------------------------------ *
* *
* Setup_EMIF_CS2_NandFlash_8Bit( ) *
* Setup Async-EMIF for NAND Flash *
* *
* ------------------------------------------------------------------------ */
hotmenu
Setup_EMIF_CS2_NandFlash_8Bit( )
{
#define NAND_CMD *( unsigned char* )( 0x42080000 )
#define CMD_RESET 0xff
GEL_TextOut( "Setup EMIF CS2 - NAND Flash (8-bit bus)... " );
/* NAND Flash settings ( @ 99MHz or below ) */
setup_aemif( EMIF_CS2, 0x028442a8, NO_NAND_FLASH );
/* Reset Flash memory to Read Mode */
NAND_CMD = CMD_RESET;
GEL_TextOut( "[Done]\n" );
}
menuitem "DaVinci HD Boot Mode";
/* ------------------------------------------------------------------------ *
* *
* Boot_Mode_Reader( ) *
* Read and Print boot mode *
* *
* ------------------------------------------------------------------------ */
hotmenu
Boot_Mode_Reader( )
{
#define SYS_BOOTCFG *( unsigned int* )( 0x01c40014 )
int dsp_boot = ( SYS_BOOTCFG >> 17 ) & 1;
int pci_enable = ( SYS_BOOTCFG >> 16 ) & 1;
int voltage_adjust = ( SYS_BOOTCFG >> 12 ) & 1;
int emifa_bus_width = ( SYS_BOOTCFG >> 8 ) & 1;
int boot_mode = ( SYS_BOOTCFG >> 0 ) & 0x0f;
GEL_TextOut( "\nBoot Mode Reader:\n" );
if ( boot_mode == 0 )
GEL_TextOut( " > [Boot Mode] : EMU Boot\n" );
else if ( boot_mode == 2 )
{
if ( pci_enable == 0 )
GEL_TextOut( " > [Boot Mode] : HPI-16 Boot\n" );
if ( pci_enable == 1 )
GEL_TextOut( " > [Boot Mode] : PCI Boot w/o auto init\n" );
}
else if ( boot_mode == 3 )
{
if ( pci_enable == 0 )
GEL_TextOut( " > [Boot Mode] : HPI-32 Boot\n" );
if ( pci_enable == 1 )
GEL_TextOut( " > [Boot Mode] : PCI Boot w/ auto init\n" );
}
else if ( boot_mode == 4 )
GEL_TextOut( " > [Boot Mode] : EMIFA Direct Boot\n" );
else if ( boot_mode == 6 )
GEL_TextOut( " > [Boot Mode] : I2C Boot\n" );
else if ( boot_mode == 7 )
{
if ( pci_enable == 0 )
GEL_TextOut( " > [Boot Mode] : NAND Boot\n" );
}
else if ( boot_mode == 8 )
GEL_TextOut( " > [Boot Mode] : UART0 Boot\n" );
else if ( boot_mode == 9 )
GEL_TextOut( " > [Boot Mode] : Emulation Boot\n" );
else if ( boot_mode == 10 )
GEL_TextOut( " > [Boot Mode] : VLYNQ Boot\n" );
else if ( boot_mode == 11 )
GEL_TextOut( " > [Boot Mode] : EMAC Boot\n" );
else if ( boot_mode == 14 )
GEL_TextOut( " > [Boot Mode] : SPI Boot\n" );
else
GEL_TextOut( " >>>>>> ERROR boot option not supported <<<<<<\n" );
if ( dsp_boot == 0 )
GEL_TextOut( " > [DSP BOOT] : ARM boots DSP\n" );
if ( dsp_boot == 1 )
GEL_TextOut( " > [DSP BOOT] : DSP self-boots\n" );
if ( pci_enable == 0 )
GEL_TextOut( " > [PCI] : OFF\n" );
if ( pci_enable == 1 )
GEL_TextOut( " > [PCI] : ON\n" );
if ( voltage_adjust == 0 )
GEL_TextOut( " > [Voltage Adj] : SmartReflex Disable\n" );
if ( voltage_adjust == 1 )
GEL_TextOut( " > [Voltage Adj] : SmartReflex Enable\n" );
if ( emifa_bus_width == 0 )
GEL_TextOut( " > [Bus Width] : 8-bit\n" );
if ( emifa_bus_width == 1 )
GEL_TextOut( " > [Bus Width] : 16-bit\n" );
GEL_TextOut( "\n" );
}
menuitem "DaVinci HD DSP";
/* ------------------------------------------------------------------------ *
* *
* boot_dsp_from_arm( ) *
* Boot DSP from ARM side. *
* *
* ------------------------------------------------------------------------ */
boot_dsp_from_arm( unsigned int boot_address )
{
#define DSPBOOTADDR *( unsigned int* )( 0x01c40008 )
#define PSC_MDCTL_DSP *( unsigned int* )( 0x01c41a00 + ( 4 * 1 ) )
GEL_TextOut( "Boot DSP from %x ... ",,,,, boot_address );
/*
* Step 1 - Turn DSP power on
*/
psc_change_state( 1, 3 );
/*
* Step 2 - Assert local reset
*/
PSC_MDCTL_DSP &= 0xfeff;
/*
* Step 3 - Program DSP boot address
* - Fill in memory w/ branch to self opcode
*/
DSPBOOTADDR = boot_address;
GEL_MemoryFill( boot_address, 0, 32, 0x13 );
/*
* 4. Release from reset
*/
PSC_MDCTL_DSP |= 0x0100;
GEL_TextOut( "[Done]\n" );
}
hotmenu
DSP_Boot_from_L2_ram( )
{
boot_dsp_from_arm( 0x11800000 ); // L2 RAM Memory
}
hotmenu
DSP_Boot_from_DDR2( )
{
boot_dsp_from_arm( 0x80000000 ); // DDR2 Memory
}
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