sdram.h

RMI的处理器au1200系列所用的BOOTLOAD,包括SD卡启动USB启动硬盘启动网络启动,并初始化硬件的所有参数,支持内核调试.

/*********************************************************************
 *
 * Copyright:
 *	Advanced Micro Devices, AMD. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of AMD. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, AMD 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  AMD assumes no responsibility for the maintenance and support
 *  of this software.
 *********************************************************************
 *
 * File:		sdram.h
 *
 * Purpose:		Definitions for Au1550 SDRAM Controller
 *
 *  $RCSfile: sdram.h,v $
 *  $Author: mwelk $
 *  $Revision: 1.5 $
 *  $Date: 2004/03/31 23:25:18 $
 *
***********************************************************************/
/*
 * Modifications:
 *
2004/03/30 mfw	Added SDRAM_DEBUG define switch
2004/01/17 mfw	Changed SDRAM_CS_MODE_REG[ES] to [BW] to match the data book
2003.11.21 mfw  Completed val, _GET(val) #defines for SD_CSMODE bit fields!
2003.11.21 mfw  Added PS bit to SD_GCR_B, and corrected Inverted Structure order!

*********************************************************************/

#ifndef __AU1550_MEM_H
#define __AU1550_MEM_H

//mfw 
#define __AU1550

#define __MEM_H_REV	2004_MAR_30

#undef	SDRAM_DEBUG


/* SDRAM Definitions */

	/* AU1550 SDRAM Controller Base Physical Address */
#define MEMORY_CTRL_BASE  (0x14000000)
#define SDRAM_1500_PHYSICAL_BASE  (MEMORY_CTRL_BASE)
#define SDRAM_1550_PHYSICAL_BASE  (MEMORY_CTRL_BASE + 0x800)

	// OLD Defines: Remove= SDRAM_1500_BASE and SDRAM_1550_BASE
#define SDRAM_1500_BASE  (SDRAM_1500_PHYSICAL_BASE)
#define SDRAM_1550_BASE  (SDRAM_1550_PHYSICAL_BASE)


//#define KSEG1(phy_addr)       (phy_addr | (0xA<<28))

#define SDRAM_CTRL_BASE  (KSEG1(SDRAM_1550_PHYSICAL_BASE))

	/* AU1550 SDRAM Controller Base KSEG1 Address = 0xb4000800 */
#define SDRAM_CTRL_KSEG1_BASE (KSEG1(SDRAM_1550_PHYSICAL_BASE))

#define SDRAM_CSMODE0		(0x0000)
#define SDRAM_CSMODE1		(0x0008)
#define SDRAM_CSMODE2		(0x0010)
// Reserved Bits are ZERO'd
#define	SDRAM_CSMODE_RSV	(0xCF7FF777)
#define	SDRAM_CSMODE_DFLT	(0x007FF776)


#define SDRAM_CSADDR0   	(0x0020)
#define SDRAM_CSADDR1   	(0x0028)
#define SDRAM_CSADDR2   	(0x0030)
// Reserved Bits are ZERO'd
#define	SDRAM_CSADDR_RSV	(0xF71FFFFFF)
#define	SDRAM_CSADDR_DFLT	(0x010FFFFFF)

#define SDRAM_GCR_A 		(0x0040)
// Reserved Bits are ZERO'd
#define	SDRAM_GCR_A_RSV		(0xFB33FFFF)
#define	SDRAM_GCR_A_DFLT	(0xF003FFFF)

#define SDRAM_GCR_B 		(0x0048)
// Reserved Bits are ZERO'd
#define	SDRAM_GCR_B_RSV		(0x0F0E709F)
#define	SDRAM_GCR_B_DFLT	(0x00000000)

#define SDRAM_ERR_RPT_STATUS	(0x0050)
// Reserved Bits are ZERO'd
#define	SDRAM_ERR_RPT_STATUS_RSV	(0x1300000F)
#define	SDRAM_ERR_RPT_STATUS_DFLT	(0x00000000)

#define SDRAM_OFF_ADD_REG	(0x0058)
// Reserved Bits are ZERO'd
#define	SDRAM_OFF_ADD_REG_RSV	(0xFFFFFFFF)
#define	SDRAM_OFF_ADD_REG_DFLT	(0x00000000)

#define SDRAM_STRIDE0		(0x0060)
#define SDRAM_STRIDE1		(0x0068)
#define SDRAM_STRIDE2		(0x0070)
// Reserved Bits are ZERO'd
#define	SDRAM_STRIDE0_RSV	(0xFFF077FF)
#define	SDRAM_STRIDE0_DFLT	(0x00000000)

#define	SDRAM_STRIDE_RSV	(0x000077FF)
#define	SDRAM_STRIDE_DFLT	(0x00000000)


#define SDRAM_WRITE_EXTERN_0	(0x0080)
#define SDRAM_WRITE_EXTERN_1	(0x0088)
#define SDRAM_WRITE_EXTERN_2	(0x0090)
// Reserved Bits are ZERO'd
#define	SDRAM_WRITE_EXTERN_RSV	(0xC0000FFF)
#define	SDRAM_WRITE_EXTERN_DFLT	(0x00000000)

#define SDRAM_LOAD_EXT_CMD_0	(0x00A0)
#define SDRAM_LOAD_EXT_CMD_1	(0x00A8)
#define SDRAM_LOAD_EXT_CMD_2	(0x00B0)
// Reserved Bits are ZERO'd
#define	SDRAM_LOAD_EXT_RSV	(0xC0000FFF)
#define	SDRAM_LOAD_EXT_DFLT	(0x00000000)

#define SDRAM_PRECHARGE_CMD	(0x00C0)
#define SDRAM_AUTO_REFRESH_CMD	(0x00C8)
#define SDRAM_SELF_REFRESH	(0x00D0)

//=========================================================
//      Bit definitions for Chip Select Timing Configuration Registers, Offset = 0x0000-0x0018
//===========================================
//-----------------------------------
//      External Bus Size (0=32-bit, 1=16-bit, 2=rsvd, 3=rsvd)

#define	SD_CSMODE_ES_POS	(30)
#define	SD_CSMODE_ES_MASK	(0x3)
#define	SD_CSMODE_ES(val)	((val&&SD_CSMODE_ES_MASK)<<SD_CSMODE_ES_POS)
#define	SD_CSMODE_ES_GET(val)	((val>>SD_CSMODE_ES_POS)&&SD_CSMODE_ES_MASK)

enum SD_EBSIZE {
    ES_32 = 0,			// 32 bit external bus (Default)
    ES_16,			// 16 bit external bus
    ES_R1,			// Reserved
    ES_R2			// Reserved
};

//---RESERVED FIELD--------------------------------
//      External Bus Size (0=32-bit, 1=16-bit, 2=rsvd, 3=rsvd)
#define	SD_CSMODE_EC_POS	(28)
#define	SD_CSMODE_EC_MASK	(0x3)
#define	SD_CSMODE_EC(val)	((val&&SD_CSMODE_EC_MASK)<<SD_CSMODE_EC_POS)
#define	SD_CSMODE_EC_GET(val)	((val>>SD_CSMODE_EC_POS)&&SD_CSMODE_EC_MASK)

enum SD_ERR_CODE {
    EC_32 = 0			// Reserved
};

//-----------------------------------
//      Memory Type (0=SDR, 1=DDR, 2=rsvd, 3=SyncFlash)
#define	SD_CSMODE_MT_POS	(26)
#define	SD_CSMODE_MT_MASK	(0x3)
#define	SD_CSMODE_MT(val)	((val&&SD_CSMODE_MT_MASK)<<SD_CSMODE_MT_POS)
#define	SD_CSMODE_MT_GET(val)	((val>>SD_CSMODE_MT_POS)&&SD_CSMODE_MT_MASK)

enum SD_MTYPE {
    MT_SDR = 0,			// Single Data Rate SDRAM (Default)
    MT_DDR,			// Double Data Rate SDRAM
    MT_RSVD,			// Memory Type Reserved
    MT_SYNCF			// SyncFlash
};

//-----------------------------------
//      (DDR Only) SKEW between external CAS latency and Internal Tcas
#define	SD_CSMODE_SKEW_POS	(24)
#define	SD_CSMODE_SKEW_MASK	(0x3)
#define	SD_CSMODE_SKEW(val)	((val&&SD_CSMODE_SKEW_MASK)<<SD_CSMODE_SKEW_POS)
#define	SD_CSMODE_SKEW_GET(val)	((val>>SD_CSMODE_SKEW_POS)&&SD_CSMODE_SKEW_MASK)

enum SD_SKEW {
    SKEW_NONE = 0,		// 00= No Skew
    HALF_CLOCK,			// 01= 1/2 clock
    ONE_CLOCK,			// 10= 1 clock
    SKEW_RSVD			// 11= Reserved
};

//-----------------------------------
//      Write to Precharge Time, value = 1 less than min. # Clock cycles
#define	SD_CSMODE_TWR_POS	(20)
#define	SD_CSMODE_TWR_MASK	(0x7)
#define	SD_CSMODE_TWR(val)	((val&&SD_CSMODE_TWR_MASK)<<SD_CSMODE_TWR_POS)
#define	SD_CSMODE_TWR_GET(val)	((val>>SD_CSMODE_TWR_POS)&&SD_CSMODE_TWR_MASK)

//-----------------------------------
//      Minimum Time for a complete access, value = 1 less than min. # Clock cycles
#define	SD_CSMODE_TRAS_POS	(16)
#define	SD_CSMODE_TRAS_MASK	(0xF)
#define	SD_CSMODE_TRAS(val)	((val&&SD_CSMODE_TRAS_MASK)<<SD_CSMODE_TRAS_POS)
#define	SD_CSMODE_TRAS_GET(val)	((val>>SD_CSMODE_TRAS_POS)&&SD_CSMODE_TRAS_MASK)

//-----------------------------------
//      Write to Read Turnaround Time, value = 1 less than required # mem bus Clock cycles
#define	SD_CSMODE_TWTR_POS	(14)
#define	SD_CSMODE_TWTR_MASK	(0x3)
#define	SD_CSMODE_TWTR(val)	((val&&SD_CSMODE_TWTR_MASK)<<SD_CSMODE_TWTR_POS)
#define	SD_CSMODE_TWTR_GET(val)	((val>>SD_CSMODE_TWTR_POS)&&SD_CSMODE_TWTR_MASK)

//-----------------------------------
//      RAS Precharge Time, value = 1 less than required # mem bus Clock cycles
#define	SD_CSMODE_TRP_POS	(12)
#define	SD_CSMODE_TRP_MASK	(0x3)
#define	SD_CSMODE_TRP(val)	((val&&SD_CSMODE_TRP_MASK)<<SD_CSMODE_TRP_POS)
#define	SD_CSMODE_TRP_GET(val)	((val>>SD_CSMODE_TRP_POS)&&SD_CSMODE_TRP_MASK)

//-----------------------------------
//      RAS to CAS delay for Writes, value = 1 less than required # mem bus Clock cycles
#define	SD_CSMODE_TRCD_WR_POS	(8)
#define	SD_CSMODE_TRCD_WR_MASK	(0x7)
#define	SD_CSMODE_TRCD_WR(val)	((val&&SD_CSMODE_TRCD_WR_MASK)<<SD_CSMODE_TRCD_WR_POS)
#define	SD_CSMODE_TRCD_WR_GET(val)	((val>>SD_CSMODE_TRCD_WR_POS)&&SD_CSMODE_TRCD_WR_MASK)

//-----------------------------------
//      RAS to CAS delay for Reads, value = 1 less than required # mem bus Clock cycles
#define	SD_CSMODE_TRCD_RD_POS	(4)
#define	SD_CSMODE_TRCD_RD_MASK	(0x7)
#define	SD_CSMODE_TRCD_RD(val)	((val&&SD_CSMODE_TRCD_RD_MASK)<<SD_CSMODE_TRCD_RD_POS)
#define	SD_CSMODE_TRCD_RD_GET(val)	((val>>SD_CSMODE_TRCD_RD_POS)&&SD_CSMODE_TRCD_RD_MASK)

//-----------------------------------
//      Minimum CAS latency timing
#define	SD_CSMODE_TCAS_POS	(0)
#define	SD_CSMODE_TCAS_MASK	(0x7)
#define	SD_CSMODE_TCAS(val)	((val&&SD_CSMODE_TCAS_MASK)<<SD_CSMODE_TCAS_POS)
#define	SD_CSMODE_TCAS_GET(val)	((val>>SD_CSMODE_TCAS_POS)&&SD_CSMODE_TCAS_MASK)

enum SD_CS_TCAS { CL_1_5_DDR = 0,	// 1.5 clocks (DDR Only)
    CL_2_5_DDR,			// 2.5 clocks (DDR Only)
    CL_3_5_DDR,			// 3.5 clocks (DDR Only)
    CL_2,			// 2.0 clocks
    CL_3,			// 3.0 clocks
    CL_4,			// 4.0 clocks
    CL_5,			// 5.0 clocks (Default)
    CL_6			// 6.0 clocks
};


//=========================================================
//      Bit definitions for Chip Select Address Configuration Registers, Offset = 0x0020-0x0038
//===========================================
//      Bits 31:22 of the Chip Select Comparison Mask. (Lower bits are set to zero) (DFLT = 3FF)
//-----------------------------------
#define	SD_CSADDR_CSMASK_POS	(0)
#define	SD_CSADDR_CSMASK_MASK	(0x3FF)
#define	SD_CSADDR_CSMASK(val)	((val&&SD_CSADDR_CSMASK_MASK)<<SD_CSADDR_CSMASK_POS)
#define	SD_CSADDR_CSMASK_GET(val)	((val>>SD_CSADDR_CSMASK_POS)&&SD_CSADDR_CSMASK_MASK)

//-----------------------------------
//      Bits 31:22 of the Chip Select Base Address. (Lower bits are set to zero) (DFLT = 3FF)
//-----------------------------------
#define	SD_CSADDR_CSBA_POS	(10)
#define	SD_CSADDR_CSBA_MASK	(0x3FF)
#define	SD_CSADDR_CSBA(val)	((val&&SD_CSADDR_CSBA_MASK)<<SD_CSADDR_CSBA_POS)
#define	SD_CSADDR_CSBA_GET(val)	((val>>SD_CSADDR_CSBA_POS)&&SD_CSADDR_CSBA_MASK)

//-----------------------------------
//      E bit non-zero to enable the Chip Select (DFLT = 0)
//-----------------------------------
#define	SD_CSADDR_E_POS 	(20)
#define	SD_CSADDR_E_MASK	(1)
#define	SD_CSADDR_E_BIT 	(1<<SD_CSADDR_E_POS)
#define	SD_CSADDR_E(val) 	((val&&SD_CSADDR_E_MASK)<<SD_CSADDR_E_POS)
#define	SD_CSADDR_E_GET(val) 	((val>>SD_CSADDR_E_POS)&&SD_CSADDR_E_MASK)

//-----------------------------------
//      Column Address Size in bits (DFLT = 1)
//-----------------------------------
#define	SD_CSADDR_CS_POS	(24)
#define	SD_CSADDR_CS_MASK	(0x7)
#define	SD_CSADDR_CS(val)	((val&&SD_CSADDR_CS_MASK)<<SD_CSADDR_CS_POS)
#define	SD_CSADDR_CS_GET(val)	((val>>SD_CSADDR_CS_POS)&&SD_CSADDR_CS_MASK)

enum SD_COLS {
    CS_8 = 1,			// Column Addr is 8 bits