reset_db1550.s

RMI的处理器au1200系列所用的BOOTLOAD,包括SD卡启动USB启动硬盘启动网络启动,并初始化硬件的所有参数,支持内核调试.

	beq		zero, t3, tlbloop
	nop

	/* Initialize the TLB entry */
	mtc0	t0, CP0_Index
	mtc0	zero, CP0_EntryLo0
	mtc0	zero, CP0_EntryLo1
	mtc0	zero, CP0_PageMask
	tlbwi

	/* Do it again */
	addiu	t0, t0, 1	
	bne		t0, t2, tlbloop
	nop

	/* Establish Wired (and Random) */
	mtc0	zero, CP0_Wired
	nop

/*
 * Run-time determination of the CPU, SBUS, and DDR frequency.
 * Switch S5.[2345] is utilized to encode a value an index 0 to 15.
 */
#ifdef USE_S5
	b		lookup_table
	nop

	/* Table entry is multiple of 16 words so that offset into table is
	 * simple shift of index value.
	 * Offset Description
	 * 0: 0x00: sys_cpupll value
	 * 1: 0x04: sys_powerctrl value
	 * 7: 0x08: mem_sttime0 value
	 * 8: 0x0C: mem_sttime1 value
	 * 9: 0x10: mem_sttime2 value
	 * A: 0x14: mem_sttime3 value
	 * 3: 0x1C: mem_sdconfiga value
	 * 4: 0x18: mem_sdconfigb value
	 * 2: 0x20: mem_sdmode value
	 * 5: 0x24: mem_mr0 value
	 * 6: 0x28: unused
	 * B: 0x2C: unused
	 * C: 0x30: unused
	 * D: 0x34: unused
	 * E: 0x38: unused
	 * F: 0x3C: unused
	 *
	 * When utilizing the tables, throughout this reset code, a0 will
	 * point to the selected configuration.
	 */
#undef SYS_CPUPLL
#undef SYS_POWERCTRL
#undef MEM_STTIME0
#undef MEM_STTIME1
#undef MEM_STTIME2
#undef MEM_STTIME3
#define SYS_CPUPLL		0x00
#define SYS_POWERCTRL	0x04
#define MEM_STTIME0		0x08
#define MEM_STTIME1		0x0C
#define MEM_STTIME2		0x10
#define MEM_STTIME3		0x14
#define MEM_SDCONFIGA	0x18
#define MEM_SDCONFIGB	0x1c
#define MEM_SDMODE		0x20
#define MEM_MR0			0x24

DDR_SPEEDS:
ddr_396_198_198:
	.long	33, 0, 0x40181D7, 0x00007774, 0x22080A20, 0x280E3E07, 0xD030060B, 0x0002801F, 0x05276222, 0x00000033, 0, 0, 0, 0, 0, 0
//ddr_192_96_96:
//	.long	16, 0, 0x200C0CB, 0x00001999, 0x1103C50F, 0x1406DD03, 0x403002EE, 0x0002801F, 0x04135113, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_336_168_168:
	.long	28, 0, 0x4014194, 0x00006EEC, 0x2206C9DB, 0x270C35C6, 0x703004F2, 0x0002801F, 0x04266221, 0x00000063, 0, 0, 0, 0, 0, 0
ddr_396_198_99:
	.long	33, 0, 0x40181D7, 0x00007774, 0x22080A20, 0x280E3E07, 0x40300306, 0x0002001F, 0x04135113, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_396_198_198_default:
	.long	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
ddr_492_123_123:
	.long	41, 2, 0x301010E, 0x00006220, 0x11050554, 0x1508E544, 0x9030060a, 0x0000001F, 0x04276221, 0x00000063, 0, 0, 0, 0, 0, 0
ddr_492_164_164:
	.long	41, 1, 0x4014193, 0x00006EEB, 0x2206C9DB, 0x270BF5C6, 0x80300502, 0x0002801F, 0x04266221, 0x00000063, 0, 0, 0, 0, 0, 0
ddr_492_246_123:
	.long	41, 0, 0x602025D, 0x0000BFFF, 0x330A0EE8, 0x3B0FFEC9, 0x9030060a, 0x0002001F, 0x04276221, 0x00000063, 0, 0, 0, 0, 0, 0
ddr_552_276_138:
	.long	46, 0, 0x60242E1, 0x0000BFFF, 0x440B532D, 0x4C0FFF0B, 0x503003D9, 0x0002001F, 0x04155113, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_600_150_150:
	.long	50, 2, 0x3014151, 0x00006AA8, 0x22060998, 0x260AED85, 0x70300494, 0x0002801F, 0x04256224, 0x00000033, 0, 0, 0, 0, 0, 0
ddr_600_200_100:
	.long	50, 1, 0x40181D7, 0x00007775, 0x22084A21, 0x280E7E07, 0x4030030E, 0x0002001F, 0x04135113, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_600_200_200:
	.long	50, 1, 0x40181D7, 0x00007775, 0x22084A21, 0x280E7E07, 0xA030061B, 0x0002801F, 0x04276224, 0x00000033, 0, 0, 0, 0, 0, 0
ddr_600_300_150:
	.long	50, 0, 0x70282E3, 0x0000BFFF, 0x440C5371, 0x4D0FFF4B, 0x70300494, 0x0002001F, 0x04256223, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_756_151_151:
	.long	63, 3, 0x3014192, 0x00006AA8, 0x22064999, 0x260AF186, 0x70300494, 0x0002801F, 0x04256223, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_756_189_189:
	.long	63, 2, 0x40181D6, 0x00007772, 0x2207CA1F, 0x280DBE07, 0x903005C5, 0x0002801F, 0x04276224, 0x00000033, 0, 0, 0, 0, 0, 0
ddr_756_252_126:
	.long	63, 1, 0x602029E, 0x0000BFFF, 0x330A4EE9, 0x3B0FFECA, 0x503003D9, 0x0002001F, 0x04155113, 0x00000023, 0, 0, 0, 0, 0, 0
ddr_756_378_189:
	.long	63, 0, 0x90343ED, 0x0000FFFF, 0x550F97FE, 0x5F0FFFCF, 0x903005C5, 0x0002001F, 0x04276224, 0x00000033, 0, 0, 0, 0, 0, 0

lookup_table:
	la		a0, DDR_SPEEDS
	li		t0, DB1550_BCSR_ADDR
read_switch:
	li		t1, 0x20000000 /* convert to KSEG1 */
	or		a0, a0, t1
	/* Read S5 to determine which setting, test if valid */
	lh		t1, bcsr_switches(t0)
	andi	t1, t1, 0x0078
	xori	t1, t1, 0x0078 /* invert to get user perspective of value */
	sll		t2, t1, 3
	addu	t3, a0, t2
	lw		t3, 0(t3)
	beq		zero, t3, default_config /* if cpupll is 0, use first speed setting */
	nop
	addu	a0, a0, t2
default_config:

	/* The correct table and configuration setting is pointed to by a0 */

	/*
	 * Step 10) Establish CPU PLL frequency
	 *
	 * Upon arriving here, the processor is one of these two situations:
	 * a) reset with core at 192MHz, default timing on RCE0, or
	 * b) core at previous freq, optimized timing for previous freq for RCE0
	 * Situation A happens with either hardware-, runtime-, hibernate- or
	 * wake-up reset.
	 * Situation B happens when software jumps to 0xBFC00000 to reboot.
	 *
	 * This code allows for selecting processor frequency (from a table of
	 * settings) at boot-time. To do so, the S5 dip switches selects
	 * the configuration, and the sys_cpupll, sys_powerctrl, and RCE0 are
	 * updated [here] to reflect the new frequency. These three items must
	 * be properly configured for the Au1550 to change frequency and continue
	 * fetching code from Flash on RCE0.
	 *
	 * The configuration table contains values for all registers that affect
	 * timing in some fashion.
	 *
	 */

	li		t0, AU1550_SYS_ADDR

	lw		t1, SYS_CPUPLL(a0)
	lw		t2, SYS_POWERCTRL(a0)
	li		t3, MEM_STCFG0
	lw		t4, MEM_STTIME0(a0)
#ifdef EB
	ori		t3, t3, 0x0200 /* mem_stcfg0[BE] */
#endif

	li		t5, AU1550_MEM_ADDR

	/*
	 * Reduce system bus to /4 for (large PLL jumps) and then
	 * jump to cache-aligned code which changes the frequency
	 */
	li		t6, 2
	sw		t6, sys_powerctrl(t0)
	sync
	beq		zero, zero, rampPLL
	nop

	/*
	 * Place the following code on an icache line boundary to force
	 * an icache fetch of the 8 insns below which change critical
	 * timing.
	 *
	 * If these insns are not in cache, then an icache miss
	 * results in potentially unusually-timed access to Flash,
	 * depending upon where the icache miss happens in the
	 * sequence below, which can have unpredictable results...
	 */
	.align 5
rampPLL:

	/*
	 * Update sys_cpupll, RCE0, and sys_powerctrl (order is important)
	 */
	sw		t1, sys_cpupll(t0)
	sync
	sw		t4, mem_sttime0(t5)
	sw		t3, mem_stcfg0(t5)
	nop		/* critical delay */
	nop		/* critical delay */
	sw		t2, sys_powerctrl(t0)
	sync

	/* End of critical timing code */

#else

	/*
	 * Step 10) Establish CPU PLL frequency
	 */
	li		t0, AU1550_SYS_ADDR
	li		t1, SYS_CPUPLL
	sw		t1, sys_cpupll(t0)
	sync
	nop
	nop

	/*
	 * Step 11) Establish system bus divider
	 */
	li		t1, SYS_POWERCTRL
	sw		t1, sys_powerctrl(t0)
	sync
#endif

	/*
	 * Step 12) Establish AUX PLL frequency
	 */
	li		t0, AU1550_SYS_ADDR
	li		t1, SYS_AUXPLL
	sw		t1, sys_auxpll(t0)
	sync

	/*
	 * Step 13) Start the 32kHz oscillator
	 */
	li		t1, 0x00000100
	sw		t1, sys_cntctrl(t0)
	sync

	/*
	 * Step 14) Initialize static memory controller
	 */
	li		t0, AU1550_MEM_ADDR

#ifndef USE_S5
	/* RCE0 - can not change while fetching, do so from icache */
updateRCE0:
	la		t1,updateRCE0
	cache	0x14,0(t1)
	cache	0x14,32(t1)
	li  	t1, MEM_STTIME0
#else
	lw		t1, MEM_STTIME0(a0)
#endif
	li  	t2, MEM_STCFG0
	li		t3, MEM_STADDR0
	sw		t1, mem_sttime0(t0)
	sw		t2, mem_stcfg0(t0)
	sw		t3, mem_staddr0(t0)
	sync

	/* RCE1 */
	li		t1, MEM_STCFG1
#ifndef USE_S5
	li		t2, MEM_STTIME1
#else
	lw		t2, MEM_STTIME1(a0)
#endif
	li		t3, MEM_STADDR1
	sw		t1, mem_stcfg1(t0)
	sw		t2, mem_sttime1(t0)
	sw		t3, mem_staddr1(t0)

	/* RCE2 */
	li		t1, MEM_STCFG2
#ifndef USE_S5
	li		t2, MEM_STTIME2
#else
	lw		t2, MEM_STTIME2(a0)
#endif
	li		t3, MEM_STADDR2
	sw		t1, mem_stcfg2(t0)
	sw		t2, mem_sttime2(t0)
	sw		t3, mem_staddr2(t0)

	/* RCE3 */
	li		t1, MEM_STCFG3
#ifndef USE_S5
	li		t2, MEM_STTIME3
#else
	lw		t2, MEM_STTIME3(a0)
#endif
	li		t3, MEM_STADDR3
	sw		t1, mem_stcfg3(t0)
	sw		t2, mem_sttime3(t0)
	sw		t3, mem_staddr3(t0)
	
	/* NAND */
	sw		zero, mem_stndctrl(t0)

	sync

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li		t0, AU1550_IC0_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1550_IC1_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1550_SYS_ADDR
	sw		zero, sys_freqctrl0(t0)
	sw		zero, sys_freqctrl1(t0)
	sw		zero, sys_clksrc(t0)
	sw		zero, sys_pininputen(t0)
	sync

	li		t0, AU1550_DDMA_ADDR
	sw		zero, ddma_inten(t0)
	sync

	li		t0, AU1550_USBH_ADDR
	li		t1, usbh_enable
	addu	t0, t1, t0
	sw		zero, 0(t0)
	sync

	li		t0, AU1550_USBD_ADDR
	sw		zero, usbd_enable(t0)
	sync

	li		t0, AU1550_MACEN_ADDR
	sw		zero, macen_mac0(t0)
	sw		zero, macen_mac1(t0)
	sync

  	li		t0, AU1550_UART0_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1550_UART1_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1550_UART3_ADDR
	sw		zero, uart_enable(t0)
	sync
	
	li		t0, AU1550_PSC0_ADDR
	sw		zero, psc_enable(t0)
	sync

	li		t0, AU1550_PSC1_ADDR
	sw		zero, psc_enable(t0)
	sync

	li		t0, AU1550_PSC2_ADDR
	sw		zero, psc_enable(t0)
	sync

	li		t0, AU1550_PSC3_ADDR
	sw		zero, psc_enable(t0)
	sync

	li		t0, AU1550_CRYPTO_ADDR
	sw		zero, crypt_enable(t0)
	sync

	/*
	 * Step 16) Determine cause of reset
	 */
	/* wait 10mS to debounce external signals */
	li		t1, MEM_1MS*10
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1550_SYS_ADDR
	lw		t1, sys_wakesrc(t0)

	/* Clear sys_wakemsk to prevent false events */
	sw		zero, sys_wakemsk(t0)
	sync

	/* Clear sys_wakesrc */
	//sw		zero, sys_wakesrc(t0)
	sync

	/* Check for Hibernate Reset first */
	andi	t2, t1, 0x04
	bne		zero, t2, hibernatereset
	nop

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne		zero, t2, hardwarereset
	nop

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne		zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	beq		zero, zero, runtimereset
	nop

/************************************************************************/

hardwarereset:
runtimereset:
hibernatereset:
	/*
	 * Step 1) Initialize DRAM
	 * Step 2) Initialize board
	 * Step 3) Invoke application
	 */
	bal 	initDRAM
	nop 
   	bal		initBOARD
	nop
	beq		zero, zero, alldone
	nop	 

sleepwakeup:
	/*
	 * Step 1) Wakeup DRAM
	 * Step 2) Initialize board
	 * Step 3) Resume application
	 */
  	bal		wakeupDRAM	
	nop
	bal		initBOARD
	nop
 	la		t0, AU1550_SYS_ADDR
	lw		sp, sys_scratch0(t0)
	lw		ra, sys_scratch1(t0)
	jr		ra
	nop

/*************************************************************************/