reset_db1550.s

RMI的处理器au1200系列所用的BOOTLOAD,包括SD卡启动USB启动硬盘启动网络启动,并初始化硬件的所有参数,支持内核调试.

/*********************************************************************
 * Copyright:
 *	Advanced Micro Devices, AMD. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
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 *  otherwise under any patents or trademarks of AMD. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, AMD 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  AMD assumes no responsibility for the maintenance and support
 *  of this software.
 ********************************************************************/

/*

This file represents all the activities necessary to bring
the Au1550 out of reset. It sets all Au1550 resources to
known, usually disabled and safe, state.

This is an example startup file, tailored for the DBAu1550
reference board. DBAu1550-specific items are commented as
such, but in general are confined to the CPU endian
selection and memory controller values.

*/


/********************************************************************/

/*
 * MIPS ABI register defintions
 */
#define zero	$0
#define v0		$2
#define v1		$3
#define a0		$4
#define a1		$5
#define a2		$6
#define a3		$7
#define t0		$8
#define t1		$9
#define t2		$10
#define t3		$11
#define t4		$12
#define t5		$13
#define t6		$14
#define t7		$15
#define s0		$16
#define s1		$17
#define s2		$18
#define s3		$19
#define s4		$20
#define s5		$21
#define s6		$22
#define s7		$23
#define t8		$24
#define t9		$25
#define k0		$26
#define k1		$27
#define gp		$28
#define sp		$29
#define fp		$30
#define ra		$31

/********************************************************************/

/*
 * Au1550 CP0 registers
 */
#define CP0_Index		$0
#define CP0_Random		$1
#define CP0_EntryLo0	$2
#define CP0_EntryLo1	$3
#define CP0_Context		$4
#define CP0_PageMask	$5
#define CP0_Wired		$6
#define CP0_BadVAddr	$8
#define CP0_Count		$9
#define CP0_EntryHi		$10
#define CP0_Compare		$11
#define CP0_Status		$12
#define CP0_Cause		$13
#define CP0_EPC			$14
#define CP0_PRId		$15
#define CP0_Config		$16
#define CP0_Config0		$16
#define CP0_Config1		$16,1
#define CP0_LLAddr		$17
#define CP0_WatchLo		$18
#define CP0_IWatchLo	$18,1
#define CP0_WatchHi		$19
#define CP0_IWatchHi	$19,1
#define CP0_Scratch		$22
#define CP0_Debug		$23
#define CP0_DEPC		$24
#define CP0_PerfCnt		$25
#define CP0_PerfCtrl	$25,1
#define CP0_DTag		$28
#define CP0_DData		$28,1
#define CP0_ITag		$29
#define CP0_IData		$29,1
#define CP0_ErrorEPC	$30
#define CP0_DESave		$31

/********************************************************************/

/*
 * Au1550 base addresses (in KSEG1 region)
 */
#define AU1550_MEM_ADDR		0xB4000000
#define AU1550_SRAM_ADDR	0xB4001000
#define AU1550_DDMA_ADDR	0xB4003000
#define AU1550_PCI_ADDR		0xB4005000
#define AU1550_CRYPTO_ADDR  0xB4008000
#define AU1550_USBH_ADDR    0xB4020000
#define AU1550_USBD_ADDR    0xB0200000
#define AU1550_IC0_ADDR     0xB0400000
#define AU1550_PSC2_ADDR    0xB0A00000
#define AU1550_PSC3_ADDR    0xB0B00000
#define AU1550_UART0_ADDR   0xB1100000
#define AU1550_UART1_ADDR   0xB1200000
#define AU1550_UART3_ADDR   0xB1400000
#define AU1550_GPIO2_ADDR	0xB1700000
#define AU1550_IC1_ADDR     0xB1800000
#define AU1550_SYS_ADDR		0xB1900000
#define AU1550_PSC0_ADDR    0xB1A00000
#define AU1550_PSC1_ADDR	0xB1B00000

#define AU1550_MACEN_ADDR	0xB0520000

/*
 * Au1550 memory controller register offsets
 */
#define mem_sdmode0		    0x0800
#define mem_sdmode1		    0x0808
#define mem_sdmode2		    0x0810
#define mem_sdaddr0	    	0x0820
#define mem_sdaddr1	    	0x0828
#define mem_sdaddr2	    	0x0830
#define mem_sdconfiga		0x0840
#define mem_sdconfigb		0x0848
#define mem_sdstat		    0x0850
#define mem_sderraddr		0x0858
#define mem_sdstride0		0x0860
#define mem_sdstride1		0x0868
#define mem_sdstride2		0x0870
#define mem_sdwrmd0 		0x0880
#define mem_sdwrmd1 		0x0888
#define mem_sdwrmd2 		0x0890
#define mem_sdprecmd  	    0x08C0
#define mem_sdautoref  	    0x08C8
#define mem_sdsref  	    0x08D0

#define mem_stcfg0		    0x1000
#define mem_sttime0		    0x1004
#define mem_staddr0		    0x1008
#define mem_stcfg1		    0x1010
#define mem_sttime1		    0x1014
#define mem_staddr1		    0x1018
#define mem_stcfg2		    0x1020
#define mem_sttime2		    0x1024
#define mem_staddr2		    0x1028
#define mem_stcfg3		    0x1030
#define mem_sttime3		    0x1034
#define mem_staddr3		    0x1038
#define mem_stndctrl		0x1100


/*
 * Au1550 peripheral register offsets
 */
#define ddma_inten			0x000C
#define psc_enable		    0x0004		
#define crypt_enable	    0x0080		
#define usbh_enable		    0x0007FFC
#define usbd_enable		    0x0058
#define macen_mac0		    0x0000		
#define macen_mac1		    0x0004
#define uart_enable		    0x0100
		
#define ic_cfg0clr		    0x0044
#define ic_cfg1clr		    0x004C
#define ic_cfg2clr		    0x0054
#define ic_srcset		    0x0058
#define ic_assignset	    0x0060
#define ic_wakeclr		    0x006C
#define ic_maskclr		    0x0074
#define ic_risingclr	    0x0078
#define ic_fallingclr	    0x007C
#define ic_testbit		    0x0080

#define sys_scratch0	    0x0018
#define sys_scratch1	    0x001c
#define sys_cntctrl		    0x0014
#define sys_freqctrl0	    0x0020
#define sys_freqctrl1	    0x0024
#define sys_clksrc		    0x0028
#define sys_pinfunc		    0x002C
#define sys_wakemsk		    0x0034
#define sys_powerctrl	    0x003C
#define sys_endian		    0x0038
#define sys_wakesrc		    0x005C
#define sys_cpupll		    0x0060
#define sys_auxpll		    0x0064
#define sys_trioutclr	    0x0100
#define sys_outputset		0x0108
#define sys_outputclr	    0x010C
#define sys_pininputen	    0x0110

#define gpio2_dir		    0x0000
#define gpio2_output	    0x0008
#define gpio2_pinstate	    0x000C
#define gpio2_inten		    0x0010
#define gpio2_enable	    0x0014

#define pci_cmem			0x0000
#define pci_config			0x0004
#define pci_b2bmask_cch		0x0008
#define pci_b2bbase0_venid	0x000C
#define pci_b2bbase1_id		0x0010
#define pci_mwmask_dev		0x0014
#define pci_mwbase_rev_ccl	0x0018
#define pci_err_addr		0x001C
#define pci_spec_intack		0x0020
#define pci_id				0x0100
#define pci_statcmd			0x0104
#define pci_classrev		0x0108
#define pci_hdrtype			0x010C
#define pci_mbar			0x0110
#define pci_timeout			0x0140

/********************************************************************/

/*
 * DBAu1550-specific values
 * NOTE: All values are for operation at 396MHz, SD=2
 */
#define SYS_CPUPLL		33	/* 396Mhz */
#define SYS_POWERCTRL	0	/* SD=2   */
#define SYS_AUXPLL		32	/* 384MHz for PCI/USB */

#define DB1550_BCSR_ADDR 0xAF000000

/* RCE0: AMD 29LV256M MirrorBit Flash
 *
 * Field Flash - 120ns
 *    Ta tRC 120ns yields 24 clocks - 1
 *   Tpm tPACC 40ns yields 8 clocks - 1
 *  Tcsw tCS 0ns
 *   Twp tWP 35ns yields 7 clocks - 1
 *  Tcsh MAX(tCH 0ns, tDF 25ns) yields 5 clocks - 1
 *  Twcs tCH 0ns
 */
#define MEM_STCFG0	0x00000003
#define MEM_STADDR0	0x11803E00
#define MEM_STTIME0	0x040181D7

/* RCE1: NAND Samsung K9F1208UOA */
#define MEM_STCFG1	0x00400005
#define MEM_STADDR1	0x12000FFF
#define MEM_STTIME1	0x00007774

/* RCE2: CPLD Board Logic */
#define MEM_STCFG2	0x00000040
#define MEM_STADDR2	0x10C03f00
#define MEM_STTIME2	0x22080a20

/* RCE3: PCMCIA 250ns */
#define MEM_STCFG3	0x00000002
#define MEM_STADDR3	0x10000000
#define MEM_STTIME3	0x280E3E07

/*
 * SDCS0 - 64MB MT46V16M16TG-58
 * SDCS1 - 64MB	MT46V16M16TG-58
 * SDCS2 - 64MB MT46V16M16TG-58
 *
 * 198MHz DDR settings (CL=3 requires internal tcas=3.5clk with .5clk skew)
 */
#define MEM_SDCONFIGA_DDR	0xD030060B
#define MEM_SDCONFIGB_DDR	0x0002801F
#define MEM_SDMODE_DDR		0x05276222
#define MEM_SDADDR0_DDR		0xE21003F0 
#define MEM_SDADDR1_DDR		0xE21043F0
#define MEM_SDADDR2_DDR		0xE21083F0
#define MEM_MR0_DDR			0x00000033
#define MEM_MR1_DDR			0x40000000 /* normal, not reduced, drive strength */
#define MEM_MR2_DDR			0x80000000
#define MEM_MR3_DDR			0xC0000000

#define MEM_SDCONFIGA_E 0x08000000 /* refresh enable */
#define MEM_SDCONFIGB_BA (1<<7)

#ifdef USE_S5
/* Conservative timing to work with all processor frequencies for reading S5 */
#undef MEM_STTIME2
#define MEM_STTIME2	0xFFFFFFFF
#endif

#define MEM_1MS			((396000000/1000000) * 1000)

/*
 * Board CPLD registers
 */
#define bcsr_switches		0x08

/********************************************************************/
/********************************************************************/
/********************************************************************/
/********************************************************************/

	.text
	.set noreorder
	.set mips32

	/*
	 * Step 1) Establish CPU endian mode.
	 * Db1550-specific:
	 * Switch S5.1 Off(bit7 reads 1) is Little Endian
	 * Switch S5.1 On (bit7 reads 0) is Big Endian
	 */
	li		t0, AU1550_MEM_ADDR
	li		t1, MEM_STCFG2
	sw		t1, mem_stcfg2(t0)
	li		t1, MEM_STTIME2
	sw		t1, mem_sttime2(t0)
	li		t1, MEM_STADDR2
	sw		t1, mem_staddr2(t0)
	sync

	li		t0, DB1550_BCSR_ADDR
	lh		t1, bcsr_switches(t0)
	andi	t1,t1,0x80
	beq		zero,t1,big_endian
	nop

	/* Set to little endian */

little_endian:	

	/* Change Au1 core to little endian */
	li		t0, AU1550_SYS_ADDR
	li		t1, 1
	sw		t1, sys_endian(t0)
	sync
	mfc0	t2, CP0_Config
	mtc0	t2, CP0_Config
	nop
	nop

	/* Big Endian is default so nothing to do but fall through */

big_endian:

	/*
	 * NOTE: Config0[BE] now reflects endian mode
	 */

	/*
	 * Step 2) Establish Status Register
	 * (set BEV, clear ERL, clear EXL, clear IE)
	 */
	li		t1, 0x00400000
	mtc0	t1, CP0_Status

	/*
	 * Step 3) Establish CP0 Config0
	 * (set OD, set K0=3)
	 */
	li		t1, 0x00080003
	mtc0	t1, CP0_Config0

	/*
	 * Step 4) Disable Watchpoint facilities
	 */
	li t1, 0x00000000
	mtc0	t1, CP0_WatchLo
	mtc0	t1, CP0_IWatchLo

	/*
	 * Step 5) Disable the performance counters
	 */
	mtc0	zero, CP0_PerfCtrl
	nop

	/*
	 * Step 6) Establish EJTAG Debug register
	 */
	mtc0	zero, CP0_Debug
	nop

	/*
	 * Step 7) Establish Cause
	 * (set IV bit)
	 */
	li		t1, 0x00800000
	mtc0	t1, CP0_Cause

	/*
	 * Step 8) Initialize the caches
	 */
	li		t0, (16*1024)
	li		t1, 32
	li		t2, 0x80000000
	addu	t3, t0, t2
cacheloop:
	cache	0, 0(t2)
	cache	1, 0(t2)
	addu	t2, t1
	bne		t2, t3, cacheloop
	nop

	/* Run from cacheable space now */
	bal		cachehere
	nop
cachehere:
	li		t1, ~0x20000000 /* convert to KSEG0 */
	and		t0, ra, t1
	addi	t0, 5*4			/* 5 insns beyond cachehere */
	jr		t0
	nop

	/*
	 * Step 9) Initialize the TLB
	 */
	li		t0, 0		 	# index value
	li		t1, 0x00000000 	# entryhi value
	li		t2, 32		   	# 32 entries
tlbloop:
	/* Probe TLB for matching EntryHi */
	mtc0	t1, CP0_EntryHi
	tlbp
	nop

	/* Examine Index[P], 1=no matching entry */
	mfc0	t3, CP0_Index
	li		t4, 0x80000000
	and		t3, t4, t3
	addiu	t1, t1, 1		# increment t1 (asid)