platform.h

RMI的处理器au1200系列所用的BOOTLOAD,包括SD卡启动USB启动硬盘启动网络启动,并初始化硬件的所有参数,支持内核调试.

#ifndef PB1550
#define PB1550
#endif
#define AU1550

/*
 * Frequency info
 */
#define CPU_FREQUENCY	(12000000 * 33)
#define CPU_SD			2

// Hardware is designed such that:
// PCI Connector 1 (Right) is PCI_AD[24] for IDSEL# (device 13)
// PCI Connector 1 INTA# -> Au1550 PCI_INTA#
// PCI Connector 1 INTB# -> Au1550 PCI_INTB#
// PCI Connector 1 INTC# -> Au1550 PCI_INTC#
// PCI Connector 1 INTD# -> Au1550 PCI_INTD#
// PCI Connector 2 (Left) is PCI_AD[23] for IDSEL# (device 12)
// PCI Connector 2 INTA# -> Au1550 PCI_INTB#
// PCI Connector 2 INTB# -> Au1550 PCI_INTC#
// PCI Connector 2 INTC# -> Au1550 PCI_INTD#
// PCI Connector 2 INTD# -> Au1550 PCI_INTA#
#define PLATFORM_PCI_IRQ_ROUTE_CODE \
	if (dev == 13)					\
	{switch (irqpin) {				\
	case 1: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 1); break; \
	case 2: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 2); break; \
	case 4: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 5); break; \
	case 8: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 6); break; \
	default: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 0); break; \
	} } else						\
	if (dev == 12)					\
	{switch (irqpin) {				\
	case 1: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 2); break; \
	case 2: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 5); break; \
	case 4: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 6); break; \
	case 8: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 8 + 1); break; \
	default: pciWrCfg8(bus, dev, func, PCI_CFG_TYPE00_INTERRUPT_LINE, 0); break; \
	} }

/*
 * Overlay data structure of the Pb1550 board registers.
 * Registers located at physical 0x0F0000xx, KSEG1 0xAF0000xx
 */
#define BCSR_PHYS_ADDR 0x0F000000

#ifndef ASSEMBLER
typedef volatile struct {
    /*00 */ uint16 whoami;
    uint16 reserved0;
    /*04 */ uint16 status;
    uint16 reserved1;
    /*08 */ uint16 switches;
    uint16 reserved2;
    /*0C */ uint16 resets;
    uint16 reserved3;
    /*10 */ uint16 pcmcia;
    uint16 reserved4;
    /*14 */ uint16 pci;
    uint16 reserved5;
    /*18 */ uint16 leds;
    uint16 reserved6;
    /*1C */ uint16 system;
    uint16 reserved7;

} BCSR;
static BCSR *bcsr = (BCSR *) KSEG1(BCSR_PHYS_ADDR);
#endif

/*
 * Register bit definitions for the BCSRs
 */
#define BCSR_WHOAMI_DCID	0x000F
#define BCSR_WHOAMI_CPLD	0x00F0
#define BCSR_WHOAMI_BOARD	0x0F00

#define BCSR_STATUS_PCMCIA0VS	0x0003
#define BCSR_STATUS_PCMCIA1VS	0x000C
#define BCSR_STATUS_PCMCIA0FI	0x0010
#define BCSR_STATUS_PCMCIA1FI	0x0020
#define BCSR_STATUS_SWAPBOOT	0x0040
#define BCSR_STATUS_SRAMWIDTH	0x0080
#define BCSR_STATUS_FLASHBUSY	0x0100
#define BCSR_STATUS_ROMBUSY		0x0200
#define BCSR_STATUS_USBOTGID	0x0800
#define BCSR_STATUS_U0RXD		0x1000
#define BCSR_STATUS_U1RXD		0x2000
#define BCSR_STATUS_U3RXD		0x8000

#define BCSR_SWITCHES_OCTAL		0x00FF
#define BCSR_SWITCHES_DIP_1		0x0080
#define BCSR_SWITCHES_DIP_2		0x0040
#define BCSR_SWITCHES_DIP_3		0x0020
#define BCSR_SWITCHES_DIP_4		0x0010
#define BCSR_SWITCHES_DIP_5		0x0008
#define BCSR_SWITCHES_DIP_6		0x0004
#define BCSR_SWITCHES_DIP_7		0x0002
#define BCSR_SWITCHES_DIP_8		0x0001
#define BCSR_SWITCHES_ROTARY	0x0F00

#define BCSR_RESETS_PHY0	0x0001
#define BCSR_RESETS_PHY1	0x0002
#define BCSR_RESETS_DC	0x0004
#define BCSR_RESETS_WSC	0x2000
#define BCSR_RESETS_SPISEL	0x4000
#define BCSR_RESETS_DMAREQ	0x8000

#define BCSR_PCMCIA_PC0VPP		0x0003
#define BCSR_PCMCIA_PC0VCC		0x000C
#define BCSR_PCMCIA_PC0DRVEN	0x0010
#define BCSR_PCMCIA_PC0RST		0x0080
#define BCSR_PCMCIA_PC1VPP		0x0300
#define BCSR_PCMCIA_PC1VCC		0x0C00
#define BCSR_PCMCIA_PC1DRVEN	0x1000
#define BCSR_PCMCIA_PC1RST		0x8000
#define BCSR_PCMCIA_PC0VPP_N(N)	(BCSR_PCMCIA_PC0VPP & (N<<0))
#define BCSR_PCMCIA_PC0VCC_N(N)	(BCSR_PCMCIA_PC0VCC & (N<<2))
#define BCSR_PCMCIA_PC1VPP_N(N)	(BCSR_PCMCIA_PC1VPP & (N<<8))
#define BCSR_PCMCIA_PC1VCC_N(N)	(BCSR_PCMCIA_PC1VCC & (N<<10))

#define BCSR_PCI_M66EN			0x0001
#define BCSR_PCI_M33			0x0100
#define BCSR_PCI_EXTERNARB		0x0200
#define BCSR_PCI_GPIO200RST		0x0400
#define BCSR_PCI_CLKOUT			0x0800
#define BCSR_PCI_CFGHOST		0x1000

#define BCSR_LEDS_DECIMALS		0x00FF
#define BCSR_LEDS_LED0			0x0100
#define BCSR_LEDS_LED1			0x0200
#define BCSR_LEDS_LED2			0x0400
#define BCSR_LEDS_LED3			0x0800

#define BCSR_SYSTEM_VDDI		0x001F
#define BCSR_SYSTEM_POWEROFF	0x4000
#define BCSR_SYSTEM_RESET		0x8000

#define PCMCIA_PC0_INSERT_IRQ	0
#define PCMCIA_PC1_INSERT_IRQ	1
#define PCMCIA_PC0_STAT_CHG_IRQ	203
#define PCMCIA_PC1_STAT_CHG_IRQ	205
#define PCMCIA_PC0_IRQ			201
#define PCMCIA_PC1_IRQ			202
#define PCMCIA_PC0_VS(X)		((X&BCSR_STATUS_PCMCIA0VS)>>0)
#define PCMCIA_PC1_VS(X)		((X&BCSR_STATUS_PCMCIA1VS)>>2)

#define FLASH_AMD_MIRRORBIT
#define FLASH_START_PHYS_ADDRESS	0x1E000000
#define FLASH_END_PHYS_ADDRESS		0x1FFFFFFF
#define FLASH_BLOCK_SIZE			0x00020000
#define FLASH_ALTERNATE_ADDR		0xBBC00000

#define NAND_FORCE_CE_GPIO	206

#define IDE_PHYS_ADDR		0x0C800000
#define SPI_PSC_BASE        PSC0_PHYS_ADDR
#define AC97_PSC_BASE       PSC1_PHYS_ADDR
#define SMBUS_PSC_BASE      PSC2_PHYS_ADDR
#define I2S_PSC_BASE        PSC3_PHYS_ADDR