reset_ficmmp.s

RMI的处理器au1200系列所用的BOOTLOAD,包括SD卡启动USB启动硬盘启动网络启动,并初始化硬件的所有参数,支持内核调试.

 
#define PB1200_BCSR_ADDR	0xAD800000

#define bcsr_whoami			0x00 
#define bcsr_status			0x04
#define bcsr_switches		0x08
#define bcsr_resets			0x0C
#define bcsr_pcmcia			0x10
#define bcsr_board			0x14
#define bcsr_leds			0x18
#define bcsr_system			0x1C
#define bcsr_icer			0x20
#define bcsr_iser			0x24
#define bcsr_icmr			0x28
#define bcsr_ismr			0x2C
#define bcsr_ssr			0x30
#define bcsr_isr			0x34  */

/*
 * Uncomment the following to place SRAM (instead of DDR) at 0x00000000
 * This creates the following:
 * 0x00000000 for 64M : RCE2, with SRAM @ 0x00000000
 * 0x04000000 for 64M : DDR rank1 (DDR rank0 is disabled)
 * NOTE: Must also change YAMON/arch/include/pb1000.h to match.
 */
//#define USE_SRAM
#ifdef USE_SRAM
#undef MEM_STADDR2
#define MEM_STADDR2	0x10003f00
#undef MEM_SDADDR0_DDR
#define MEM_SDADDR0_DDR 0x00000000
#undef PB1200_BCSR_ADDR
#define PB1200_BCSR_ADDR  0xA1800000
#endif

/********************************************************************/
/********************************************************************/
/********************************************************************/
/********************************************************************/

	.text
	.set noreorder
	.set mips32

	/*
	 * Step 1) Establish CPU endian mode.
	 * Pb1200-specific:
	 * Switch S12.1 Off(bit7 reads 1) is Little Endian
	 * Switch S12.1 On (bit7 reads 0) is Big Endian
	 */
	li		t0, AU1200_MEM_ADDR
	li		t1, MEM_STCFG2
	sw		t1, mem_stcfg2(t0)
	li		t1, MEM_STTIME2
	sw		t1, mem_sttime2(t0)
	li		t1, MEM_STADDR2
	sw		t1, mem_staddr2(t0)
	sync

/*	li		t0, PB1200_BCSR_ADDR
	lh		t1, bcsr_switches(t0)
	andi	t1, t1, 0x80
	beq		zero, t1, big_endian
	nop	 */

	/* Set to little endian */

little_endian:	

	/* Change Au1 core to little endian */
	li		t0, AU1200_SYS_ADDR
	li		t1, 1
	sw		t1, sys_endian(t0)
	sync
	mfc0	t2, CP0_Config
	mtc0	t2, CP0_Config
	nop
	nop

	/* Big Endian is default so nothing to do but fall through */

big_endian:

	/*
	 * NOTE: Config0[BE] now reflects endian mode
	 */

	/*
	 * Step 2) Establish Status Register
	 * (set BEV, clear ERL, clear EXL, clear IE)
	 */
	li		t1, 0x00400000
	mtc0	t1, CP0_Status

	/*
	 * Step 3) Establish CP0 Config0
	 * (set OD, set K0=3)
	 */
	li		t1, 0x00080003
	mtc0	t1, CP0_Config0

	/*
	 * Step 4) Disable Watchpoint facilities
	 */
	li t1, 0x00000000
	mtc0	t1, CP0_WatchLo
	mtc0	t1, CP0_IWatchLo

	/*
	 * Step 5) Disable the performance counters
	 */
	mtc0	zero, CP0_PerfCtrl
	nop

	/*
	 * Step 6) Establish EJTAG Debug register
	 */
	mtc0	zero, CP0_Debug
	nop

	/*
	 * Step 7) Establish Cause
	 * (set IV bit)
	 */
	li		t1, 0x00800000
	mtc0	t1, CP0_Cause

	/*
	 * Step 8) Initialize the caches
	 */
	li		t0, (16*1024)
	li		t1, 32
	li		t2, 0x80000000
	addu	t3, t0, t2
cacheloop:
	cache	0, 0(t2)
	cache	1, 0(t2)
	addu	t2, t1
	bne		t2, t3, cacheloop
	nop

	/* Run from cacheable space now */
	bal		cachehere
	nop
cachehere:
	li		t1, ~0x20000000 /* convert to KSEG0 */
	and		t0, ra, t1
	addi	t0, 5*4			/* 5 insns beyond cachehere */
	jr		t0
	nop

	/*
	 * Step 9) Initialize the TLB
	 */
	li		t0, 0		 	# index value
	li		t1, 0x00000000 	# entryhi value
	li		t2, 32		   	# 32 entries
tlbloop:
	/* Probe TLB for matching EntryHi */
	mtc0	t1, CP0_EntryHi
	tlbp
	nop

	/* Examine Index[P], 1=no matching entry */
	mfc0	t3, CP0_Index
	li		t4, 0x80000000
	and		t3, t4, t3
	addiu	t1, t1, 1		# increment t1 (asid)
	beq		zero, t3, tlbloop
	nop

	/* Initialize the TLB entry */
	mtc0	t0, CP0_Index
	mtc0	zero, CP0_EntryLo0
	mtc0	zero, CP0_EntryLo1
	mtc0	zero, CP0_PageMask
	tlbwi

	/* Do it again */
	addiu	t0, t0, 1	
	bne		t0, t2, tlbloop
	nop

	/* Establish Wired (and Random) */
	mtc0	zero, CP0_Wired
	nop

/*
 * Run-time determination of the CPU, SBUS, and DDR frequency.
 * Switch S12.[2345] is utilized to encode a value an index 0 to 15.
 */
#ifdef USE_S12
	b		lookup_table
	nop

	/* Table entry is multiple of 16 words so that offset into table is
	 * simple shift of index value.
	 * Offset Description
	 * 0: 0x00: sys_cpupll value
	 * 1: 0x04: sys_powerctrl value
	 * 2: 0x08: mem_stcfg0 value
	 * 3: 0x0C: mem_sttime0 value
	 * 4: 0x10: mem_stcfg1 value
	 * 5: 0x14: mem_sttime1 value
	 * 6: 0x18: mem_stcfg2 value
	 * 7: 0x1C: mem_sttime2 value
	 * 8: 0x20: mem_stcfg3 value
	 * 9: 0x24: mem_sttime3 value
	 * A: 0x28: mem_staltime value
	 * B: 0x2C: mem_sdconfiga value
	 * C: 0x30: mem_sdconfigb value
	 * D: 0x34: mem_sdmode value
	 * E: 0x38: mem_mr0 value
	 * F: 0x3C: mem_mr1 value
	 *
	 * When utilizing the tables, throughout this reset code, a0 will
	 * point to the selected configuration.
	 */
#undef SYS_CPUPLL
#undef SYS_POWERCTRL
#undef MEM_STCFG0
#undef MEM_STTIME0
#undef MEM_STCFG1
#undef MEM_STTIME1
#undef MEM_STCFG2
#undef MEM_STTIME2
#undef MEM_STCFG3
#undef MEM_STTIME3
#undef MEM_STALTIME
#define SYS_CPUPLL		0x00
#define SYS_POWERCTRL	0x04
#define MEM_STCFG0		0x08
#define MEM_STTIME0		0x0C
#define MEM_STCFG1		0x10
#define MEM_STTIME1		0x14
#define MEM_STCFG2		0x18
#define MEM_STTIME2		0x1C
#define MEM_STCFG3		0x20
#define MEM_STTIME3		0x24
#define MEM_STALTIME	0x28
#define MEM_SDCONFIGA	0x2C
#define MEM_SDCONFIGB	0x30
#define MEM_SDMODE		0x34
#define MEM_MR0			0x38
#define MEM_MR1			0x3C

DDR1_SPEEDS:
ddr1_192_96_96:
	.long 16, 0, 0x002D0043, 0x0330C0CA, 0x00440045, 0x00003332, 0x422D00C6, 0x02218409, 0x00040042, 0x13061AC3, 0x00000001, 0x306002EE, 0x8002000C, 0x00131113, 0x00000022, 0x40000000
ddr1_336_168_168:
	.long 28, 0, 0x002D0043, 0x05514152, 0x00440045, 0x00006664, 0x862D00C6, 0x1442CC0F, 0x00040042, 0x220C3506, 0x00000001, 0x30B00520, 0x8002000C, 0x01262224, 0x00000032, 0x40000000
ddr1_396_198_99:
	.long 33, 0, 0x002D0043, 0x06618195, 0x00440045, 0x00007774, 0x862D00C6, 0x14434C12, 0x00040042, 0x280E3E07, 0x00000001, 0x30600305, 0x0002000C, 0x00131113, 0x00000022, 0x40000000
ddr1_396_198_198:
	.long 33, 0, 0x002D0043, 0x06618195, 0x00440045, 0x00007774, 0x862D00C6, 0x14434C12, 0x00040042, 0x280E3E07, 0x00000001, 0x30D0060A, 0x8002000C, 0x01272224, 0x00000032, 0x40000000
ddr1_492_123_123:
	.long 41, 2, 0x002D0043, 0x0441010D, 0x00440045, 0x00004443, 0x662D00C6, 0x1332080B, 0x00040042, 0x180823A4, 0x00000001, 0x308003C0, 0x8002000C, 0x01141113, 0x00000022, 0x40000000
ddr1_492_164_164:
	.long 41, 1, 0x002D0043, 0x05514152, 0x00440045, 0x00006664, 0x862D00C6, 0x1442CC0F, 0x00040042, 0x210C34E6, 0x00000001, 0x30B00501, 0x8002000C, 0x01262224, 0x00000032, 0x40000000
ddr1_492_246_123:
	.long 41, 0, 0x202D0043, 0x0882021B, 0x00440045, 0x00009996, 0xCA2D00C6, 0x26645017, 0x00040042, 0x3214578A, 0x00000001, 0x308003C0, 0x0002000C, 0x01141113, 0x00000022, 0x40000000
ddr1_552_276_138:
	.long 46, 0, 0x202D0043, 0x0992425E, 0x00440045, 0x0000BBB6, 0xCA2D00C6, 0x2664D41A, 0x00040042, 0x3816606B, 0x00000001, 0x30900436, 0x0002000C, 0x01252223, 0x00000022, 0x40000000
ddr1_600_150_150:
	.long 50, 2, 0x002D0043, 0x05514150, 0x00440045, 0x00005553, 0x662D00C6, 0x1332880E, 0x00040042, 0x1E0A2C85, 0x00000001, 0x30A00493, 0x8002000C, 0x01252224, 0x00000032, 0x40000000
ddr1_600_200_100:
	.long 50, 1, 0x002D0043, 0x06618195, 0x00440045, 0x00007774, 0x862D00C6, 0x14434C12, 0x00040042, 0x280E3E07, 0x00000001, 0x3060030D, 0x0002000C, 0x00131113, 0x00000022, 0x40000000
ddr1_600_200_200:
	.long 50, 1, 0x002D0043, 0x06618195, 0x00440045, 0x00007774, 0x862D00C6, 0x14434C12, 0x00040042, 0x280E3E07, 0x00000001, 0x30D0061A, 0x8002000C, 0x01272224, 0x00000032, 0x40000000
ddr1_600_300_150:
	.long 50, 0, 0x202D0043, 0x0AA282A0, 0x00440045, 0x0000BBB7, 0xEA2D00C6, 0x2775141C, 0x00040042, 0x3D18692C, 0x00000001, 0x30A00493, 0x0002000C, 0x01252224, 0x00000032, 0x40000000
ddr1_756_189_189:
	.long 63, 2, 0x002D0043, 0x06618194, 0x00440045, 0x00007774, 0x862D00C6, 0x14434C11, 0x00040042, 0x260E3DC7, 0x00000001, 0x30D005C4, 0x8002000C, 0x01272224, 0x00000032, 0x40000000
ddr1_756_252_126:
	.long 63, 1, 0x202D0043, 0x0882021B, 0x00440045, 0x0000AAA6, 0xCA2D00C6, 0x26645417, 0x00040042, 0x331457AA, 0x00000001, 0x308005C4, 0x0002000C, 0x01151113, 0x00000022, 0x40000000
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0

DDR2_SPEEDS:
ddr2_396_198_198: // Samsung DDR2-400 devices
	.long 33, 0, 0x002D0043, 0x06618195, 0x00440045, 0x00007774, 0x862D00C6, 0x14434C12, 0x00040042, 0x280E3E07, 0x00000001, 0x3140060A, 0xA002000C, 0x01272224, 0x00000432, 0x40000400
ddr2_504_252_252: // Samsung DDR2-400 devices over-clocked
	.long 42, 0, 0x002D0043, 0x0882021B, 0x00440045, 0x0000AAA6, 0xCA2C00C6, 0x26645417, 0x00040042, 0x331457AA, 0x00000001, 0x31A007B0, 0xA002000C, 0x021A3335, 0x00000242, 0x40000400
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
	.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0

lookup_table:
	la		a0, DDR1_SPEEDS
	/* check for DDR1 vs DDR2 */
	li		t0, PB1200_BCSR_ADDR
	lh		t1, bcsr_whoami(t0)
	andi	t1, t1, 0x0100
	beq		zero, t1, read_switch
	nop
	la		a0, DDR2_SPEEDS
read_switch:
	li		t1, 0x20000000 /* convert to KSEG1 */
	or		a0, a0, t1
	/* Read S12 to determine which setting, test if valid */
	lh		t1, bcsr_switches(t0)
	andi	t1, t1, 0x0078
	xori	t1, t1, 0x0078 /* invert to get user perspective of value */
	sll		t2, t1, 3
	addu	t3, a0, t2
	lw		t3, 0(t3)
	beq		zero, t3, default_config
	nop
	addu	a0, a0, t2
default_config:

	/* The correct table and configuration setting is pointed to by a0 */

	/*
	 * Step 10) Establish CPU PLL frequency
	 *
	 * Upon arriving here, the processor is one of these two situations:
	 * a) reset with core at 192MHz, default timing on RCE0, or
	 * b) core at previous freq, optimized timing for previous freq for RCE0
	 * Situation A happens with either hardware-, runtime-, hibernate- or
	 * wake-up reset.
	 * Situation B happens when software jumps to 0xBFC00000 to reboot.
	 *
	 * This code allows for selecting processor frequency (from a table of
	 * settings) at boot-time. To do so, the S12 dip switches select
	 * the configuration, and the sys_cpupll, sys_powerctrl, and RCE0 are
	 * updated [here] to reflect the new frequency. These three items must
	 * be properly configured for the Au1200 to change frequency and continue
	 * fetching code from Flash on RCE0.
	 *
	 * The configuration table contains values for all registers that affect
	 * timing in some fashion.
	 */

	li		t0, AU1200_SYS_ADDR

	lw		t1, SYS_CPUPLL(a0)
	lw		t2, SYS_POWERCTRL(a0)
	lw		t3, MEM_STCFG0(a0)
	lw		t4, MEM_STTIME0(a0)
#ifdef EB
	ori		t3, t3, 0x0200 /* mem_stcfg0[BE] */
#endif

	li		t5, AU1200_MEM_ADDR

	/*
	 * Reduce system bus to /4 for (large PLL jumps) and then
	 * jump to cache-aligned code which changes the frequency
	 */
	li		t6, 2
	sw		t6, sys_powerctrl(t0)
	sync
	beq		zero, zero, rampPLL
	nop

	/*
	 * Place the following code on an icache line boundary to force
	 * an icache fetch of the 8 insns below which change critical
	 * timing.
	 *
	 * If these insns are not in cache, then an icache miss
	 * results in potentially unusually-timed access to Flash,
	 * depending upon where the icache miss happens in the
	 * sequence below, which can have unpredictable results...
	 */
	.align 5
rampPLL:

	/*
	 * Update sys_cpupll, RCE0, and sys_powerctrl (order is important)
	 */
	sw		t1, sys_cpupll(t0)
	sync
	sw		t4, mem_sttime0(t5)
	sw		t3, mem_stcfg0(t5)
	sw		t2, sys_powerctrl(t0)
	sync

	/* End of critical timing code */

#else
	/*
	 * Step 10) Establish CPU PLL frequency
	 */
	li		t0, AU1200_SYS_ADDR
	li		t1, SYS_CPUPLL
	sw		t1, sys_cpupll(t0)
	sync
	nop
	nop

	/*
	 * Step 11) Establish system bus divider
	 */
	li		t1, SYS_POWERCTRL
	sw		t1, sys_powerctrl(t0)
	sync
#endif

	/*
	 * Step 12) Establish AUX PLL frequency
	 */
	li		t0, AU1200_SYS_ADDR
	li		t1, SYS_AUXPLL
	sw		t1, sys_auxpll(t0)
	sync

	/*
	 * Step 13) Start the 32kHz oscillator
	 */
	li		t1, 0x00000100
	sw		t1, sys_cntctrl(t0)
	sync

	/*
	 * Step 14) Initialize static memory controller
	 */
	li		t0, AU1200_MEM_ADDR
#ifndef USE_S12
	li		t1, MEM_STCFG0
	li		t2, MEM_STTIME0
#else
	lw		t1, MEM_STCFG0(a0)
	lw		t2, MEM_STTIME0(a0)
#endif
	li		t3, MEM_STADDR0
#ifdef EB
	ori		t1, t1, 0x0200 /* mem_stcfg0[BE] */
#endif
	sw		t1, mem_stcfg0(t0)
	sw		t2, mem_sttime0(t0)
	sw		t3, mem_staddr0(t0)
	sync

	/* RCE1 */
#ifndef USE_S12
	li		t1, MEM_STCFG1
	li		t2, MEM_STTIME1
#else
	lw		t1, MEM_STCFG1(a0)
	lw		t2, MEM_STTIME1(a0)
#endif
	li		t3, MEM_STADDR1
	sw		t1, mem_stcfg1(t0)
	sw		t2, mem_sttime1(t0)
	sw		t3, mem_staddr1(t0)

	/* RCE2 */
#ifndef USE_S12
	li		t1, MEM_STCFG2
	li		t2, MEM_STTIME2
#else
	lw		t1, MEM_STCFG2(a0)
	lw		t2, MEM_STTIME2(a0)
#endif
	li		t3, MEM_STADDR2
	sw		t1, mem_stcfg2(t0)
	sw		t2, mem_sttime2(t0)
	sw		t3, mem_staddr2(t0)

	/* RCE3 */
#ifndef USE_S12
	li		t1, MEM_STCFG3
	li		t2, MEM_STTIME3
#else
	lw		t1, MEM_STCFG3(a0)
	lw		t2, MEM_STTIME3(a0)
#endif
	li		t3, MEM_STADDR3
	sw		t1, mem_stcfg3(t0)
	sw		t2, mem_sttime3(t0)
	sw		t3, mem_staddr3(t0)

	/* Address latch */
#ifndef USE_S12
	li		t1, MEM_STALTIME
#else
	lw		t1, MEM_STALTIME(a0)
#endif
	sw		t1, mem_staltime(t0)
	sync

	/* NAND */
	sw		zero, mem_stndctrl(t0)
	sync

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li		t0, AU1200_IC0_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1200_IC1_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)