📄 reset_ficmmp.s
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/*********************************************************************
*
* Copyright:
* Advanced Micro Devices, AMD. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of AMD. This
* software is provided on an "AS IS" basis and without warranty.
*
* To the maximum extent permitted by applicable law, AMD
* DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
* PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
* SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
* ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
* INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
* LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* AMD assumes no responsibility for the maintenance and support
* of this software.
********************************************************************/
/*
This file represents all the activities necessary to bring
the Au1200 out of reset. It sets all Au1200 resources to
known, usually disabled and safe, state.
This is an example startup file, tailored for the PbAu1200
reference board. PbAu1200-specific items are commented as
such, but in general are confined to the CPU endian
selection and memory controller values.
*/
/********************************************************************/
/*
* MIPS ABI register defintions
*/
#define zero $0
#define v0 $2
#define v1 $3
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define k0 $26
#define k1 $27
#define gp $28
#define sp $29
#define fp $30
#define ra $31
/********************************************************************/
/*
* Au1200 CP0 registers
*/
#define CP0_Index $0
#define CP0_Random $1
#define CP0_EntryLo0 $2
#define CP0_EntryLo1 $3
#define CP0_Context $4
#define CP0_PageMask $5
#define CP0_Wired $6
#define CP0_BadVAddr $8
#define CP0_Count $9
#define CP0_EntryHi $10
#define CP0_Compare $11
#define CP0_Status $12
#define CP0_Cause $13
#define CP0_EPC $14
#define CP0_PRId $15
#define CP0_Config $16
#define CP0_Config0 $16
#define CP0_Config1 $16,1
#define CP0_LLAddr $17
#define CP0_WatchLo $18
#define CP0_IWatchLo $18,1
#define CP0_WatchHi $19
#define CP0_IWatchHi $19,1
#define CP0_Scratch $22
#define CP0_Debug $23
#define CP0_DEPC $24
#define CP0_PerfCnt $25
#define CP0_PerfCtrl $25,1
#define CP0_DTag $28
#define CP0_DData $28,1
#define CP0_ITag $29
#define CP0_IData $29,1
#define CP0_ErrorEPC $30
#define CP0_DESave $31
/********************************************************************/
/*
* Au1200 base addresses (in KSEG1 region)
*/
#define AU1200_MEM_ADDR 0xB4000000
#define AU1200_MAEBE_ADDR 0xB4010000
#define AU1200_MAEFE_ADDR 0xB4012000
#define AU1200_DDMA_ADDR 0xB4003000
#define AU1200_MSR_ADDR 0xB4020000
#define AU1200_OTG_ADDR 0xB4020020
#define AU1200_OHC_ADDR 0xB4020100
#define AU1200_EHC_ADDR 0xB4020200
#define AU1200_DEV_ADDR 0xB4022000
#define AU1200_CIM_ADDR 0xB4004000
#define AU1200_LCD_ADDR 0xB5000000
#define AU1200_IC0_ADDR 0xB0400000
#define AU1200_UART0_ADDR 0xB1100000
#define AU1200_UART1_ADDR 0xB1200000
#define AU1200_SWC_ADDR 0xB1100100
#define AU1200_GPIO2_ADDR 0xB1700000
#define AU1200_IC1_ADDR 0xB1800000
#define AU1200_SYS_ADDR 0xB1900000
#define AU1200_PSC0_ADDR 0xB1A00000
#define AU1200_PSC1_ADDR 0xB1B00000
#define AU1200_AES_ADDR 0xB0300000
#define AU1200_SD0_ADDR 0xB0600000
#define AU1200_SD1_ADDR 0xB0680000
/*
* Au1200 memory controller register offsets
*/
#define mem_sdmode0 0x0800
#define mem_sdmode1 0x0808
#define mem_sdaddr0 0x0820
#define mem_sdaddr1 0x0828
#define mem_sdconfiga 0x0840
#define mem_sdconfigb 0x0848
#define mem_sdstat 0x0850
#define mem_sdwrmd0 0x0880
#define mem_sdwrmd1 0x0888
#define mem_sdprecmd 0x08C0
#define mem_sdautoref 0x08C8
#define mem_sdsref 0x08D0
#define mem_stcfg0 0x1000
#define mem_sttime0 0x1004
#define mem_staddr0 0x1008
#define mem_stcfg1 0x1010
#define mem_sttime1 0x1014
#define mem_staddr1 0x1018
#define mem_stcfg2 0x1020
#define mem_sttime2 0x1024
#define mem_staddr2 0x1028
#define mem_stcfg3 0x1030
#define mem_sttime3 0x1034
#define mem_staddr3 0x1038
#define mem_staltime 0x1040
#define mem_stndctrl 0x1100
/*
* Au1200 peripheral register offsets
*/
#define ddma_inten 0x000C
#define psc_enable 0x0004
#define uart_enable 0x0100
#define maebe_ctlenable 0x0700
#define cim_enable 0x0000
#define lcd_screen 0x0004
#define swcnt_control 0x0000
#define msr_mcfg 0x0004
#define sd_enable 0x000C
#define aes_status 0x0000
#define ic_cfg0clr 0x0044
#define ic_cfg1clr 0x004C
#define ic_cfg2clr 0x0054
#define ic_srcset 0x0058
#define ic_assignset 0x0060
#define ic_wakeclr 0x006C
#define ic_maskclr 0x0074
#define ic_risingclr 0x0078
#define ic_fallingclr 0x007C
#define ic_testbit 0x0080
#define sys_scratch0 0x0018
#define sys_scratch1 0x001c
#define sys_cntctrl 0x0014
#define sys_freqctrl0 0x0020
#define sys_freqctrl1 0x0024
#define sys_clksrc 0x0028
#define sys_pinfunc 0x002C
#define sys_wakemsk 0x0034
#define sys_powerctrl 0x003C
#define sys_endian 0x0038
#define sys_wakesrc 0x005C
#define sys_cpupll 0x0060
#define sys_auxpll 0x0064
#define sys_trioutclr 0x0100
#define sys_outputset 0x0108
#define sys_outputclr 0x010C
#define sys_pininputen 0x0110
#define gpio2_dir 0x0000
#define gpio2_output 0x0008
#define gpio2_pinstate 0x000C
#define gpio2_inten 0x0010
#define gpio2_enable 0x0014
/********************************************************************/
/*
* PbAu1200-specific values
* NOTE: All values are for operation at 396MHz, SD=2
*/
#define SYS_CPUPLL 33 /* 396Mhz */
#define SYS_POWERCTRL 0 /* SD=2 */
#define SYS_AUXPLL 8 /* 96MHz for LCD */
/*
* With SBUS of 198MHz and mem_stcfg0[TS]=0, static bus controller
* clock period is 5ns
*/
/* Address Latch Timing - SN74LVC16374ADVG latch on rising edge of ALE
Tah=000 (0 clocks)
Tlw=000 (1+0 clocks)
Tasu=001 (1 clocks) Latch needs 3ns
*/
#define MEM_STALTIME 0x00000001
/* RCE0: 128Mb Spansion S29GL128N11T MirrorBit Flash - 110ns, Vio=3V
Data sheet S29GLxxxN_MirrorBit.pdf data May 13, 2004
Tcsoe= (1+0 clocks) data sheet specs MAX(tCE 110ns - tOE 25ns), choose 5ns for stable address, AS=1
Toecs= (0+0 clocks) data sheet specs 0ns, AH=0
Twcs= (1+0 clocks) data sheet specs 0ns for tCH
Tcsh= (1+6 clocks) data sheet specs MAX(tWPH 30ns, tCEH 35ns)
Tcsoff= (1+6 clocks) match Tcsh
Twp= (1+6 clocks) data sheet specs 35ns for tWP
Tcsw= (1+0 clocks) data sheet specs 0ns for tCS
Tpm= (1+6 clocks) data sheet specs 35ns for tPACC
Ta= (1+21 clocks) data sheet specs 110ns for tRC
mem_stcfg0: 0000 0000 0010 1101 0000 0000 0100 0011 : 0x002D0043
Tcsoe=000 (see above)
Toecs=000 (see above)
AH=0 (not needed)
NW=0 (n/a)
AS=1 (setup needed)
S=0 (asynchronous)
DE=1 (de-assert)
MBSa=1
MBC=0
TA=1 (Tcsh for reads and writes)
DIV=000 (n/a)
ALD=0 (address latch enable)
AV=0 (no address visibility)
BE=0 (little endian)
TS=0 (asynchronous operation)
EW=0 (n/a)
MBSb=1
BS=0 (n/a)
PM=0 (disable page mode)
RO=0 (writable)
DTY=3 (NOR Flash)
mem_sttime0: 0000 0110 0110 0001 1000 0001 1001 0101 : 0x06618195
Twcs=000
Tcsh=0110
Tcsoff=110
Twp=000110
Tcsw=0000
Tpm=0110
Ta=010101
*/
#define MEM_STCFG0 0x002D0043 /* 16-bit little-endian */
#define MEM_STTIME0 0x06618195
#define MEM_STADDR0 0x11F03FC0
/* RCE1: LAN91C111 */
#define MEM_STCFG1 0x862D00C0
#define MEM_STTIME1 0x14434C12
#define MEM_STADDR1 0x10C03fe0
/* RCE2: IDE PIOmode4
Tcsoe=MAX( 0ns, 20ns, 25ns, 0ns) = (1+4 clocks) AS=1
Toecs=MAX( 0ns, 5ns, 10ns, 0ns) = (1+1 clocks) AH=1
Twcs=MAX( 0ns, 5ns, 10ns, 0ns) = (1+1 clocks)
Tcsh=MAX(10ns, 20ns, 25ns, 0ns) = (1+4 clocks)
Tcsoff=MAX(10ns, 20ns, 25ns, 0ns) = (1+4 clocks)
Twp=MAX(15ns, 20ns, 70ns, 50ns) = (1+13 clocks)
Tcsw=MAX(10ns, 20ns, 20ns, 0ns) = (1+3 clocks)
Tpm=MAX( 0ns, 0ns, 25/0ns, 0ns) = (1+0 clocks)
Ta=MAX( 5ns, 35ns, 95ns, 80ns) = (1+18 clocks)
mem_stcfg2: 1000 0110 0010 1101 0000 0000 1100 0110 : 0x862D00C6
Tcsoe=100 (see above)
Toecs=001 (see above)
AH=1 (hold needed)
NW=0 (n/a)
AS=1 (setup needed)
S=0 (asynchronous)
DE=1 (de-assert)
MBSa=1
MBC=0
TA=1 (Tcsh for reads and writes)
BE=0 (little endian)
TS=0 (asynchronous operation)
EW=1 (absolutely needed)
MBSb=1
BS=0 (n/a)
PM=0 (disable page mode)
RO=0 (writable)
DTY=6 (IDE)
mem_sttime2: 0001 0100 0100 0011 0100 1100 0001 0010 : 0x14434C12
Twcs=001
Tcsh=0100
Tcsoff=100
Twp=001101
Tcsw=0011
Tpm=0000
Ta=010010
*/
#define MEM_STCFG2 0x862D00C6
#define MEM_STTIME2 0x14434C12
#define MEM_STADDR2 0x10C83fe0
/* RCE3: Control Latch for Power and Clocks */
#define MEM_STCFG3 0x002D0040
#define MEM_STTIME3 0x14434C12
#define MEM_STADDR3 0x10D03fe0
#define MEM_SDCONFIGA_E 0x80000000
#define MEM_SDCONFIGB_BB (1<<19)
#define MEM_SDCONFIGB_BA (1<<7)
/* PB1200-DDR1
* SDCS0 - 128MB Micron MT46V32M16TG-5B (8Mbit x 16 x 4bank x 2devices)
With a DDR clock of 198MHz (sdconfigb[CR]=1), DDR clock period is 5ns
mem_sdmode: 0000 0001 0010 0111 0010 0010 0010 0100 : 0x01272224
Twtr=001 (1+1 clocks) data sheet specs 2 clocks for tWTR
Twr=010 (1+2 clocks) data sheet specs 15ns for tWR
Tras=0111 (1+7 clocks) data sheet specs 40ns for tRAS
Trp=010 (1+2 clocks) data sheet specs 15ns for tRP
Trcdwr=010 (1+2 clocks) data sheet specs 15ns for tRCD
Trcdrd=010 (1+2 clocks) data sheet specs 15ns for tRCD
Tcas=100 (CL=3 ) data sheet specs CL=3 for 133mhz < tCLK <= 200mhz
mem_sdaddr: 0010 0010 0001 0000 0000 0011 1111 0000 : 0x231003F0
BR=0 (bank,row,col)
RS=10 (13 row)
CS=010 (9 col)
E=1 (enabled)
CSBA=0000000000 (0x00000000)
CSMASK=1111110000 (0xFC000000)
mem_sdconfiga: 0011 0000 1101 0000 0000 0110 0000 1010 : 0x30D0060A
E=0 (refresh disable)
CE=11 (both clocks enabled)
RPT=00 (1 refresh per cycle)
Trc=1101 (1+13 clocks) data sheet specs 55ns for tRC, 70ns for tRFC
REF=0x60A (1562 clocks) data sheet specs 7.8125us intervals (8K rows in 64ms)
mem_sdconfigb: 1000 0000 0000 0010 0000 0000 0000 0000 : 0x8002000C
CR=1 (1:1)
BW=0 (32bit wide bus)
MT=0 (DDR1)
PSEL=0 (addr 10 for auto precharge)
C2=0 (core lowest priority)
AC=00 (default)
HP=0 (no half-pll mode)
PM=00 (no power modes)
CKECNT=00 (n/a)
BB=0 (normal)
DS=1 (full drive strength)
FS=0 (normal)
PDX=00 (n/a)
CKEmin=00 (n/a)
CB=0 (normal)
TXARD=000 (n/a)
BA=0 (no block)
TXSR=001100 (1+12 * 16=208 > 200 clocks)
mem_sdwrmd:
Mode Register 0: 0000 0000 0011 0010 : 0x0032
mode=000000 normal operation
CL=011 CL=3
BT=0 sequential burst type
BL=010 burst length of 4
Mode Register 1: 0000 0000 0000 0000 : 0x0000
Normal drive strength
Mode Register 2: 0x0000
Mode Register 3: 0x0000
*/
#define MEM_SDMODE0_DDR 0x01272224
//#define MEM_SDMODE1_DDR 0x01272224
#define MEM_SDADDR0_DDR 0x231003E0
//#define MEM_SDADDR1_DDR 0x221043F0
#define MEM_SDCONFIGA_DDR 0x30D0060A
#define MEM_SDCONFIGB_DDR 0x8002000C
#define MEM_MR0_DDR 0x00000032
#define MEM_MR1_DDR 0x40000000
#define MEM_MR2_DDR 0x80000000
#define MEM_MR3_DDR 0xC0000000
/* PB1200-DDR2 (DDR2-400)
* SDCS0 - 128MB Samsung K4T51163QB-GCCC (8Mbit x 16 x 4bank x 2devices)
With a DDR clock of 198MHz (sdconfigb[CR]=1), DDR clock period is 5ns
mem_sdmode: 0000 0001 0010 0111 0010 0010 0010 0100 : 0x01272224
Twtr=001 (1+1 clocks) data sheet specs 10ns for tWTR
Twr=010 (1+2 clocks) data sheet specs 15ns for tWR
Tras=0111 (1+7 clocks) data sheet specs 40ns for tRAS
Trp=010 (1+2 clocks) data sheet specs 15ns for tRP
Trcdwr=010 (1+2 clocks) data sheet specs 15ns for tRCD
Trcdrd=010 (1+2 clocks) data sheet specs 15ns for tRCD
Tcas=100 (CL=3 ) data sheet specs CL=3 for 400mhz
mem_sdaddr: 0010 0011 0001 0000 0000 0011 1110 0000 : 0x231003E0
BR=0 (bank,row,col)
RS=10 (13 row)
CS=011 (10 col)
E=1 (enabled)
CSBA=0000000000 (0x00000000)
CSMASK=1111100000 (0xF8000000)
mem_sdconfiga: 0011 0001 0100 0000 0000 0110 0000 1010 : 0x3140060A
E=0 (refresh disable)
CE=11 (both clocks enabled)
RPT=00 (1 refresh per cycle)
Trc=010100 (1+20 clocks) data sheet specs 55ns for tRC, 105ns for tRFC
REF=0x60A (1562 clocks) data sheet specs 7.8125us intervals (8K rows in 64ms)
mem_sdconfigb: 1010 0000 0000 0010 0000 0000 0000 0000 : 0xA002000C
CR=1 (1:1)
BW=0 (32bit wide bus)
MT=1 (DDR2)
PSEL=0 (addr 10 for auto precharge)
C2=0 (core lowest priority)
AC=00 (default)
HP=0 (no half-pll mode)
PM=00 (no power modes)
CKECNT=00 (n/a)
BB=0 (normal)
DS=1 (full drive strength)
FS=0 (normal)
PDX=00 (n/a)
CKEmin=00 (n/a ?)
CB=0 (normal)
TXARD=000 (n/a)
BA=0 (no block)
TXSR=001100 (1+12 * 16=208 > 200 clocks)
mem_sdwrmd:
Mode Register 0: 0000 0100 0011 0010 : 0x0432
PD=0 Fast Exit
WR=010 3 Clocks
DLL=0 Normal
TM=0 Normal
CL=011 CL=3
BT=0 sequential burst type
BL=010 burst length of 4
Mode Register 1: 0000 0100 0000 0000 : 0x0400
OUT=0 Normal drive strength
RDQS=0 Disable
DQS=1 Disable
OCD=000 Not supported
RTT=00 Disable
AL=00 0
ODS=0 100%
DLL=0 Normal/Enable
Mode Register 2: 0x0000
Mode Register 3: 0x0000
*/
#define MEM_SDMODE0_DDR2 0x01272224
#define MEM_SDMODE1_DDR2 0x00000000
#define MEM_SDADDR0_DDR2 0x231003E0
#define MEM_SDADDR1_DDR2 0x00000000
#define MEM_SDCONFIGA_DDR2 0x3140060A
#define MEM_SDCONFIGB_DDR2 0xA002000C
#define MEM_MR0_DDR2 0x00000432
#define MEM_MR1_DDR2 0x40000400
#define MEM_MR2_DDR2 0x80000000
#define MEM_MR3_DDR2 0xC0000000
#define MEM_1MS ((396000000/1000000) * 1000)
/*
* No CPLD for FIC RDK Board CPLD registers
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