magic_reg_defs.h

realview下的一个arm9的bootloader烧录器.支持norflash读写

#define CKSW3_FR_D4      (unsigned int) 0x00000008
#define CKSW9_FR_SW8     (unsigned int) 0x00000200
#define HCLK_DIV_1       (unsigned int) 0x00100000
#define HCLK_DIV_2       (unsigned int) 0x00200000
#define HCLK_DIV_CLR     (unsigned int) 0x00f00000
#define CKSW0_CLR        (unsigned int) 0x00000001
#define CKSW1_CLR        (unsigned int) 0x00000002
#define CKSW2_CLR        (unsigned int) 0x00000004
#define CKSW3_CLR        (unsigned int) 0x00000008
#define CKSW7_CLR        (unsigned int) 0x00000080
#define CKSW8_CLR        (unsigned int) 0x00000100
#define CKSW9_CLR        (unsigned int) 0x00000200
#define D5_CLR           (unsigned int) 0xff000000
#define D5_DIV_13        (unsigned int) 0x0d000000
#define D5_DIV_EN        (unsigned int) 0x80000000
#define D5_DIV_EN_CLR    (unsigned int) 0x80000000
#define D4_CLR           (unsigned int) 0x00ff0000
#define D4_DIV_2         (unsigned int) 0x00020000
#define D4_DIV_EN        (unsigned int) 0x00800000
#define D4_DIV_EN_CLR    (unsigned int) 0x00800000

//A9,  201.5MHz = DIVR1 + DIVF31 + DIVQ2,  means 26MHz /1 *31 /2^2
//A9,  175.5MHz = DIVR1 + DIVF27 + DIVQ2,  means 26MHz /1 *27 /2^2  (175.5MHz => 5.698ns,  87.75MHz => 11.396ns)
//----- 38.4 ns /27 *4 = 5.6888   5.6888*2=11.376
//----- 38.46ns /27 *4 = 5.698    5.698 *2=11.396
//----- 39.2 ns /27 *4 ~ 5.8      5.8   *2=11.6  (25.5MHz, 86.2MHz, 172.4MHz)
//??,  104.0MHz = DIVR1 + DIVF32 + DIVQ3,  means 26MHz /1 *32 /2^8
//USB,  48.0MHz = DIVR1 + DIVF32 + DIVQ3,  means 26MHz /1 *32 /2^3 = 104MHz  => d5 (/13) = 8MHz
//                DIVR1 + DIVF96 + DIVQ3,  means  8MHz /1 *96 /2^3 = 96MHz   => d4 (/2)  =48MHz    "26M(*4)/13(*12)/2"
//                
//DIVR output 5MHz~900MHz 			(binary value + 1) --- bit[7:0]
#define PLL_DIVR1        (unsigned int) 0x00000000
#define PLL_DIVR2        (unsigned int) 0x00000001
//DIVF means the multiple value (500M~1000MHz)	(binary value + 1) --- bit[15:8]  =>   1e = 30+1 = 31
#define PLL_DIVF96       (unsigned int) 0x00005f00
#define PLL_DIVF32       (unsigned int) 0x00001f00
#define PLL_DIVF31       (unsigned int) 0x00001e00
#define PLL_DIVF27       (unsigned int) 0x00001a00
#define PLL_DIVF26       (unsigned int) 0x00001900
//DIVQ means the multiple value 		(2^ binary value)  --- bit[18:16]
#define PLL_DIVQ2        (unsigned int) 0x00020000
#define PLL_DIVQ3        (unsigned int) 0x00030000
//RANGE for jitter
#define PLL_RANGE10      (unsigned int) 0x00100000
#define PLL_RANGE42      (unsigned int) 0x00400000
//Others
#define PLL_FSEN         (unsigned int) 0x00800000
#define PLL_RESET        (unsigned int) 0x01000000
#define PLL_NO_RESET     (unsigned int) 0x00000000
#define PLL_BYPAS        (unsigned int) 0x02000000
#define PLL_NO_BYPAS     (unsigned int) 0x00000000
#define PLL_LOCK_INDCA   (unsigned int) 0x04000000
//#define PLL_NEED_CLR     (unsigned int) 0x00800000

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* System controller registers						     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define   cksw_reg ((volatile unsigned int *) (sysctl_base+0x000)) 
#define   pll1_reg ((volatile unsigned int *) (sysctl_base+0x004)) 
#define   pll2_reg ((volatile unsigned int *) (sysctl_base+0x008)) 
//#define pll3_reg ((volatile unsigned int *) (sysctl_base+0x00c)) 
#define   pll4_reg ((volatile unsigned int *) (sysctl_base+0x080)) 
#define   pll5_reg ((volatile unsigned int *) (sysctl_base+0x084)) 


#define reset_reg ((volatile unsigned int *) (sysctl_base+0x010)) 
#define remap_reg ((volatile unsigned int *) (sysctl_base+0x014)) 
#define iram0_pri_reg ((volatile unsigned int *) (sysctl_base+0x018)) 
#define iram1_pri_reg ((volatile unsigned int *) (sysctl_base+0x01c)) 
#define iram2_pri_reg ((volatile unsigned int *) (sysctl_base+0x020)) 
#define iram3_pri_reg ((volatile unsigned int *) (sysctl_base+0x024)) 
#define xsm_pri_reg ((volatile unsigned int *) (sysctl_base+0x028)) 
#define xfm_pri_reg ((volatile unsigned int *) (sysctl_base+0x02c)) 
#define apb_pri_reg ((volatile unsigned int *) (sysctl_base+0x030)) 
#define ahb_com_pri_reg ((volatile unsigned int *) (sysctl_base+0x034)) 
#define ahb_vdo_pri_reg ((volatile unsigned int *) (sysctl_base+0x038)) 
#define sleep_reg ((volatile unsigned int *) (sysctl_base+0x03c)) 
#define async_reg ((volatile unsigned int *) (sysctl_base+0x040)) 
#define pin_mux_reg ((volatile unsigned int *) (sysctl_base+0x044)) 
#define debug_reg ((volatile unsigned int *) (sysctl_base+0x048)) 


#define ahb_shr_gclk_reg ((volatile unsigned int *) (mis_apb_base+0x000)) 

/*****************************************************************************/
/* xsm register                                     */
/*****************************************************************************/
#define flash_reg         ((volatile unsigned *)(xsm_apb_base + 0x00))
#define psram_reg         ((volatile unsigned *)(xsm_apb_base + 0x04))
#define burst_mode_reg    ((volatile unsigned *)(xsm_apb_base + 0x08))

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* A9's Interrupt controller register                                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
//#define FIQ_SEL_REG    ((volatile unsigned *)itrc_a9_base)
//#define IRQ_SEL_REG    ((volatile unsigned *)(itrc_a9_base + 0x04))
//#define PRI_SET_1_REG  ((volatile unsigned *)(itrc_a9_base + 0x08))
//#define PRI_SET_2_REG  ((volatile unsigned *)(itrc_a9_base + 0x0C))
//#define IRQ_INDICA_REG ((volatile unsigned *)(itrc_a9_base + 0x10))
//#define FIQ_INDICA_REG ((volatile unsigned *)(itrc_a9_base + 0x14))
//#define ITR_TSTCTL_REG ((volatile unsigned *)(itrc_a9_base + 0x18))
//#define ITR_TSTDAT_REG ((volatile unsigned *)(itrc_a9_base + 0x1C))

#define A9_FIQ_SEL_REG    ((volatile unsigned *)itrc_a9_base)
#define A9_IRQ_SEL_REG    ((volatile unsigned *)(itrc_a9_base + 0x04))
#define A9_PRI_SET_1_REG  ((volatile unsigned *)(itrc_a9_base + 0x08))
#define A9_PRI_SET_2_REG  ((volatile unsigned *)(itrc_a9_base + 0x0C))
#define A9_IRQ_INDICA_REG ((volatile unsigned *)(itrc_a9_base + 0x10))
#define A9_FIQ_INDICA_REG ((volatile unsigned *)(itrc_a9_base + 0x14))
#define A9_ITR_TSTCTL_REG ((volatile unsigned *)(itrc_a9_base + 0x18))
#define A9_ITR_TSTDAT_REG ((volatile unsigned *)(itrc_a9_base + 0x1C))


#define key_itr_a9           0x00
#define hif_itr_a9           0x01
#define gpt_a9_itr_a9        0x02
#define wdt_itr_a9           0x03
#define xitr_a9              0x04
#define uart_itr_a9          0x05
#define rep_a7_itr_a9        0x06
#define simme_itr_a9         0x07
#define gpdma_itr_a9         0x08
#define vdo_itr_a9           0x09
#define abb_itr_a9           0x09
#define gea_itr_a9           0x0a
#define ahbm_itr_a9          0x0b
#define apbp_itr_a9          0x0b
#define drx_itr_a9           0x0c
#define audio_itr_a9         0x0d
#define usb_itr_a9           0x0e

#define KEYINT           0x00
#define LCMINT           0x01
#define GPTINT           0x02
#define WDTINT           0x03
#define EXTINT           0x04
#define uart_intr        0x05
#define simme_int        0x07
//#define SARINT           0x08
#define GPDMAINT           0x08
#define RTCINT           0x09
#define GEAINT           0x0a
#define DSPapbINT        0x0b
#define DRXINT	         0x0c
#define AUDIOIFINT       0x0d
#define USBINT           0x0e

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* A7's Interrupt controller register                                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define A7_FIQ_SEL_REG    ((volatile unsigned *)itrc_a7_base)
#define A7_IRQ_SEL_REG    ((volatile unsigned *)(itrc_a7_base + 0x04))
#define A7_PRI_SET_1_REG  ((volatile unsigned *)(itrc_a7_base + 0x08))
#define A7_PRI_SET_2_REG  ((volatile unsigned *)(itrc_a7_base + 0x0C))
#define A7_IRQ_INDICA_REG ((volatile unsigned *)(itrc_a7_base + 0x10))
#define A7_FIQ_INDICA_REG ((volatile unsigned *)(itrc_a7_base + 0x14))
#define A7_ITR_TSTCTL_REG ((volatile unsigned *)(itrc_a7_base + 0x18))
#define A7_ITR_TSTDAT_REG ((volatile unsigned *)(itrc_a7_base + 0x1C))


#define key_itr_a7           0x00
#define hif_itr_a7           0x01
#define gpt_a7_itr_a7        0x02
#define wdt_itr_a7           0x03
#define xitr_a7              0x04
#define uart_itr_a7          0x05
#define com_a9_itr_a7        0x06
#define simme_itr_a7         0x07
#define gpdma_itr_a7         0x08
#define abb_itr_a7           0x09
#define gea_itr_a7           0x0a
#define apbp_itr_a7          0x0b
#define ahbm_itr_a7          0x0b
#define drx_itr_a7           0x0c
#define audio_itr_a7         0x0d
#define usb_itr_a7           0x0e



/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* a9 command register                                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define a9_com0_reg       ((volatile unsigned *)(a9_com_base + 0x000))
#define a9_rep0_reg       ((volatile unsigned *)(a9_com_base + 0x004))
#define a9_com1_reg       ((volatile unsigned *)(a9_com_base + 0x008))
#define a9_rep1_reg       ((volatile unsigned *)(a9_com_base + 0x00c))
#define a9_com_ctl_reg    ((volatile unsigned *)(a9_com_base + 0x010))

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* a9 pmu register                                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define a9_gck_reg        ((volatile unsigned *)(a9_pmu_base + 0x000))
#define a9_halt_reg       ((volatile unsigned *)(a9_pmu_base + 0x004))
#define a9_remap_reg      ((volatile unsigned *)(a9_pmu_base + 0x008))

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* a7 reply register                                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define a7_rep0_reg       ((volatile unsigned *)(a7_rep_base + 0x004))
#define a7_rep1_reg       ((volatile unsigned *)(a7_rep_base + 0x00c))
#define a7_rep_ctl_reg    ((volatile unsigned *)(a7_rep_base + 0x010))

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* a7 pmu register                                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define a7_gck_reg        ((volatile unsigned *)(a7_pmu_base + 0x000))
#define a7_halt_reg       ((volatile unsigned *)(a7_pmu_base + 0x004))
#define a7_remap_reg      ((volatile unsigned *)(a7_pmu_base + 0x008))

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/