magic_reg_defs.h

来自「realview下的一个arm9的bootloader烧录器.支持norflas」· C头文件 代码 · 共 1,123 行 · 第 1/5 页

#define	USB_EP3WM_CLR	          (unsigned int) 0x00000004
#define	USB_EP3_ACK_CLR	          (unsigned int) 0x00000001 //DHskStsReg
#define USB_EP3_ACK               (unsigned int) 0x00000001

#define	USB_DMA_EN		  (unsigned int) 0x00000001
#define	USB_DMA_RX		  (unsigned int) 0x00000000
#define	USB_DMA_TX		  (unsigned int) 0x00000002
#define	USB_DMA_DIR_CLR		  (unsigned int) 0x00000002


/************************/
/* FGPIO physical meaning */
/************************/
#define	FGPIO2_GEN_IN		  (unsigned int) 0x00000000
#define	FGPIO2_GEN_OUT		  (unsigned int) 0x00000010
#define	FGPIO2_ITR_IN		  (unsigned int) 0x00000020
#define	FGPIO3_GEN_IN		  (unsigned int) 0x00000000
#define	FGPIO3_GEN_OUT		  (unsigned int) 0x00000040
#define	FGPIO3_ITR_IN		  (unsigned int) 0x00000080
#define	FGPIO4_GEN_IN		  (unsigned int) 0x00000000
#define	FGPIO4_GEN_OUT		  (unsigned int) 0x00000100
#define	FGPIO4_ITR_IN		  (unsigned int) 0x00000200
#define	FGPO2_0			  (unsigned int) 0x00000000
#define	FGPO2_1			  (unsigned int) 0x00000004
#define	FGPO3_0			  (unsigned int) 0x00000000
#define	FGPO3_1			  (unsigned int) 0x00000008
#define	FGPO4_0			  (unsigned int) 0x00000000
#define	FGPO4_1			  (unsigned int) 0x00000010

/************************/
/* MEMDMA physical meaning */
/************************/
#define PRI_SET_P_DIS	(unsigned int)	0x00000000
#define PRI_SET_P_ROT	(unsigned int)	0x00000001
#define PRI_SET_P_ROT_F1  (unsigned int) 0x00000002
#define PRI_SET_P_ROT_F12 (unsigned int) 0x00000003
#define PRI_FST_CH1	(unsigned int)	0x00000000
#define PRI_FST_CH2	(unsigned int)	0x00000004
#define PRI_FST_CH3	(unsigned int)	0x00000008
#define PRI_FST_CH4	(unsigned int)	0x0000000c
#define PRI_SEC_CH1	(unsigned int)	0x00000000
#define PRI_SEC_CH2	(unsigned int)	0x00000020
#define PRI_SEC_CH3	(unsigned int)	0x00000040
#define PRI_SEC_CH4	(unsigned int)	0x00000060
#define PRI_TRD_CH1	(unsigned int)	0x00000000
#define PRI_TRD_CH2	(unsigned int)	0x00000100
#define PRI_TRD_CH3	(unsigned int)	0x00000200
#define PRI_TRD_CH4	(unsigned int)	0x00000300
#define PRI_FUR_CH1	(unsigned int)	0x00000000
#define PRI_FUR_CH2	(unsigned int)	0x00000800
#define PRI_FUR_CH3	(unsigned int)	0x00001000
#define PRI_FUR_CH4	(unsigned int)	0x00001800

#define	CH1_FNSH_ITR	(unsigned int) 0x000000001
#define	CH2_FNSH_ITR	(unsigned int) 0x000000002
#define	CH3_FNSH_ITR	(unsigned int) 0x000000004
#define	CH4_FNSH_ITR	(unsigned int) 0x000000008

#define	CH1_PUS		(unsigned int) 0x000000001
#define	CH2_PUS		(unsigned int) 0x000000002
#define	CH3_PUS		(unsigned int) 0x000000004
#define	CH4_PUS		(unsigned int) 0x000000008
//#define	PAUSE_ALL	(unsigned int) 0x00000000f

#define	CH_BST_4	(unsigned int) 0x000000000
#define	CH_BST_8	(unsigned int) 0x000000001
#define	CH_BST_16	(unsigned int) 0x000000002
#define	CH_DEFT_AHBCOM	(unsigned int) 0x000000004
#define	CH_DEFT_AHBVDO	(unsigned int) 0x000000008
#define	CH_FLOAT_OFF	(unsigned int) 0x000000000
#define	CH_FLOAT_ON	(unsigned int) 0x000000010

/************************/
/* SDRAM physical meaning */
/************************/
//---SDM_DLL_CTL_REG
#define	DLL_CAL_EN		(unsigned int) 0x00000001
#define	DLL_CAL_RETURN		(unsigned int) 0x00000002
#define	DLL_CAL_LOCK		(unsigned int) 0x00000004
#define	DLL_CAL_ERR		(unsigned int) 0x00000008
//---SDM_SIZ_CFG_REG
#define	SDM_2_BNK		(unsigned int) 0x00000000
#define	SDM_4_BNK		(unsigned int) 0x00000001
#define	SDM_ROW_11bit		(unsigned int) 0x00000000
#define	SDM_ROW_12bit		(unsigned int) 0x00000004
#define	SDM_ROW_13bit		(unsigned int) 0x00000008
#define	SDM_ROW_14bit		(unsigned int) 0x0000000C
#define	SDM_COL_08bit		(unsigned int) 0x00000000
#define	SDM_COL_09bit		(unsigned int) 0x00000020
#define	SDM_COL_10bit		(unsigned int) 0x00000040
#define	SDM_COL_11bit		(unsigned int) 0x00000060
#define	SDM_COL_12bit		(unsigned int) 0x00000080
#define	SDM_SDR			(unsigned int) 0x00000000
#define	SDM_DDR			(unsigned int) 0x00000200
//---SDM_RFS_CTL_REG
#define	SDM_ARF_32cyc		(unsigned int) 0x0000001F
#define	SDM_ARF_780cyc		(unsigned int) 0x0000030B
#define	SDM_ARF_6240cyc	 	(unsigned int) 0x0000185F
#define	SDM_ARF_12480cyc	(unsigned int) 0x000030BF
#define	SDM_BRF_INI_2cyc	(unsigned int) 0x00010000
#define	SDM_BRF_INI_16cyc	(unsigned int) 0x000F0000
#define	SDM_BRF_OPR_1time	(unsigned int) 0x00000000
#define	SDM_BRF_OPR_8time	(unsigned int) 0x00700000
#define	SDM_BRF_OPR_16time	(unsigned int) 0x00F00000
#define	SDM_BRF_SR_8time	(unsigned int) 0x03000000
#define	SDM_BRF_SR_1Ktime	(unsigned int) 0x08000000
//---SDM_MOD_CTL_REG
#define	SDM_INIT		(unsigned int) 0x00000001
#define	SDM_MR			(unsigned int) 0x00000002
#define	SDM_EMR			(unsigned int) 0x00000004
#define	SDM_SR_ETR		(unsigned int) 0x00000008
#define	SDM_SR_EXT		(unsigned int) 0x00000000
#define	SDM_DPD_ETR		(unsigned int) 0x00000010
#define	SDM_DPD_EXT		(unsigned int) 0x00000000
#define	SDM_APD_NON		(unsigned int) 0x00000000
#define	SDM_APD_DYN_PRG		(unsigned int) 0x00000020
#define	SDM_APD_PRG_ONLY	(unsigned int) 0x00000040
//#define SDM_WAT_to_APD_1cyc	(unsigned int) 0x00000000
//#define SDM_WAT_to_APD_3cyc	(unsigned int) 0x00000200
#define	SDM_WAT_to_APD_6cyc	(unsigned int) 0x00000500
#define	SDM_WAT_to_APD_7cyc	(unsigned int) 0x00000600
#define	SDM_WAT_to_APD_8cyc	(unsigned int) 0x00000700
//---SDM_MOD_SET_REG
#define	SDM_CAS_2		(unsigned int) 0x00000020
#define	SDM_CAS_3		(unsigned int) 0x00000030
//---SDM_EXT_MOD_REG
#define	SDM_PASR_FUL		(unsigned int) 0x00000000
#define	SDM_PASR_HAF		(unsigned int) 0x00000001  /*** #define	SDM_TCSR		(unsigned int) 0x00000000 ***/
#define	SDM_DRI_STNG_FUL	(unsigned int) 0x00000000
#define	SDM_DRI_STNG_HAF	(unsigned int) 0x00000020
//---SDM_WRP_STA_REG
#define	SDM_FLUSH		(unsigned int) 0x00000001

//---SDM_AC_TIME_REG
#define	SDM_tRCD_1cyc		(unsigned int) 0x00000000
#define	SDM_tRCD_2cyc		(unsigned int) 0x00000001
#define	SDM_tRCD_3cyc		(unsigned int) 0x00000002
#define	SDM_tRCD_4cyc		(unsigned int) 0x00000003
#define	SDM_tRCD_5cyc		(unsigned int) 0x00000004
#define	SDM_tRCD_6cyc		(unsigned int) 0x00000005
#define	SDM_tRCD_7cyc		(unsigned int) 0x00000006
#define	SDM_tRCD_8cyc		(unsigned int) 0x00000007
#define	SDM_tRAS_1cyc		(unsigned int) 0x00000000
#define	SDM_tRAS_2cyc		(unsigned int) 0x00000010
#define	SDM_tRAS_3cyc		(unsigned int) 0x00000020
#define	SDM_tRAS_4cyc		(unsigned int) 0x00000030
#define	SDM_tRAS_5cyc		(unsigned int) 0x00000040
#define	SDM_tRAS_6cyc		(unsigned int) 0x00000050
#define	SDM_tRAS_7cyc		(unsigned int) 0x00000060
#define	SDM_tRAS_8cyc		(unsigned int) 0x00000070
#define	SDM_tRP_1cyc		(unsigned int) 0x00000000
#define	SDM_tRP_2cyc		(unsigned int) 0x00000100
#define	SDM_tRP_3cyc		(unsigned int) 0x00000200
#define	SDM_tRP_4cyc		(unsigned int) 0x00000300
#define	SDM_tRP_5cyc		(unsigned int) 0x00000400
#define	SDM_tRP_6cyc		(unsigned int) 0x00000500
#define	SDM_tRP_7cyc		(unsigned int) 0x00000600
#define	SDM_tRP_8cyc		(unsigned int) 0x00000700
#define	SDM_tRFC_1cyc		(unsigned int) 0x00000000
#define	SDM_tRFC_2cyc		(unsigned int) 0x00001000
#define	SDM_tRFC_3cyc		(unsigned int) 0x00002000
#define	SDM_tRFC_4cyc		(unsigned int) 0x00003000
#define	SDM_tRFC_5cyc		(unsigned int) 0x00004000
#define	SDM_tRFC_6cyc		(unsigned int) 0x00005000
#define	SDM_tRFC_7cyc		(unsigned int) 0x00006000
#define	SDM_tRFC_8cyc		(unsigned int) 0x00007000
#define	SDM_tRFC_9cyc		(unsigned int) 0x00008000
#define	SDM_tRFC_10cyc		(unsigned int) 0x00009000
#define	SDM_tRFC_11cyc		(unsigned int) 0x0000A000
#define	SDM_tRFC_12cyc		(unsigned int) 0x0000B000
#define	SDM_tRFC_13cyc		(unsigned int) 0x0000C000
#define	SDM_tRFC_14cyc		(unsigned int) 0x0000D000
#define	SDM_tRFC_15cyc		(unsigned int) 0x0000E000
#define	SDM_tRFC_16cyc		(unsigned int) 0x0000F000
#define	SDM_tXSR_1cyc		(unsigned int) 0x00000000
#define	SDM_tXSR_2cyc		(unsigned int) 0x00010000
#define	SDM_tXSR_3cyc		(unsigned int) 0x00020000
#define	SDM_tXSR_4cyc		(unsigned int) 0x00030000
#define	SDM_tXSR_5cyc		(unsigned int) 0x00040000
#define	SDM_tXSR_6cyc		(unsigned int) 0x00050000
#define	SDM_tXSR_7cyc		(unsigned int) 0x00060000
#define	SDM_tXSR_8cyc		(unsigned int) 0x00070000
#define	SDM_tXSR_9cyc		(unsigned int) 0x00080000
#define	SDM_tXSR_10cyc		(unsigned int) 0x00090000
#define	SDM_tXSR_11cyc		(unsigned int) 0x000A0000
#define	SDM_tXSR_12cyc		(unsigned int) 0x000B0000
#define	SDM_tXSR_13cyc		(unsigned int) 0x000C0000
#define	SDM_tXSR_14cyc		(unsigned int) 0x000D0000
#define	SDM_tXSR_15cyc		(unsigned int) 0x000E0000
#define	SDM_tXSR_16cyc		(unsigned int) 0x000F0000
#define	SDM_tXSR_17cyc		(unsigned int) 0x00100000
#define	SDM_tXSR_18cyc		(unsigned int) 0x00110000
#define	SDM_tXSR_19cyc		(unsigned int) 0x00120000
#define	SDM_tXSR_20cyc		(unsigned int) 0x00130000
#define	SDM_tXSR_21cyc		(unsigned int) 0x00140000
#define	SDM_tXSR_22cyc		(unsigned int) 0x00150000
#define	SDM_tXSR_23cyc		(unsigned int) 0x00160000
#define	SDM_tXSR_24cyc		(unsigned int) 0x00170000
#define	SDM_tXSR_25cyc		(unsigned int) 0x00180000
#define	SDM_tXSR_26cyc		(unsigned int) 0x00190000
#define	SDM_tXSR_27cyc		(unsigned int) 0x001A0000
#define	SDM_tXSR_28cyc		(unsigned int) 0x001B0000
#define	SDM_tXSR_29cyc		(unsigned int) 0x001C0000
#define	SDM_tXSR_30cyc		(unsigned int) 0x001D0000
#define	SDM_tXSR_31cyc		(unsigned int) 0x001E0000
#define	SDM_tXSR_32cyc		(unsigned int) 0x001F0000

/************************/
/* PLL physical meaning */
/************************/
//---0015A
#define   PLL1_CTL_REG ((volatile unsigned int *) (sysctl_base+0x004)) 
#define   PLL2_CTL_REG ((volatile unsigned int *) (sysctl_base+0x008)) 
#define   PLL4_CTL_REG ((volatile unsigned int *) (sysctl_base+0x080)) 
#define   PLL5_CTL_REG ((volatile unsigned int *) (sysctl_base+0x084)) 
#define   CKSW_REG     ((volatile unsigned int *) (sysctl_base+0x000)) 
#define   CKSW2_REG    ((volatile unsigned int *) (sysctl_base+0x088)) 

//---
#define CKSW0_FR_PLL1    (unsigned int) 0x00000000
#define CKSW0_FR_PLL2    (unsigned int) 0x00000001
#define CKSW1_FR_SW0     (unsigned int) 0x00000000
#define CKSW1_FR_32K     (unsigned int) 0x00000002
#define CKSW2_FR_26M     (unsigned int) 0x00000000
#define CKSW2_FR_SW1     (unsigned int) 0x00000004