magic_reg_defs.h

realview下的一个arm9的bootloader烧录器.支持norflash读写

/***************************************************************************
 * MODULE NAME:  magic.h
 *
 * DESCRIPTION:  0015a Platform
 * MODIFICATION: 
 *
 * STATUS:   
 ***************************************************************************/

#ifndef MAGIC_REG_DEFS_H
#define MAGIC_REG_DEFS_H

#include "common_var_types.h"

typedef volatile UINT32* REG_ADDR;

#define nor_base         0x10000000
#define psram_base       0x12000000

#define i_tcm_base       0x20000000
#define d_tcm_base       0x20008000

#define spm_base         0x20000000

#define cpu_sram_0_base  0x30000000
#define cpu_sram_1_base  0x30010000
#define cpu_sram_2_base  0x30020000
#define cpu_sram_3_base  0x30030000

#define CPUSRAM0Base     0x30000000
#define CPUSRAM1Base     0x30010000
#define CPUSRAM2Base  	 0x30020000
#define CPUSRAM3Base  	 0x30030000

#define apb_shr_base     0x40000000
#define apb_com_base     0x41000000
#define apb_dma_base     0x42000000
#define APB_DMA_BASE     0x42000000
#define apb_a9_base      0x43000000
#define APB_A9_BASE      0x43000000
#define apb_a7_base      0x44000000
#define APB_A7_BASE      0x44000000

#define hif_base         0x50000000
#define sdram_base       0x60000000
#define apb_ayc_base     0x90000000
#define vdo_ayc_base     0xa0000000

#define A7_PMU_BASE      (APB_A7_BASE+0x3000)
#define A9_PMU_BASE      (APB_A9_BASE+0x3000)

#define itrc_a9_base     (apb_a9_base+0x0000)
#define a9_com_base      (apb_a9_base+0x2000)
#define a9_pmu_base      (apb_a9_base+0x3000)

#define itrc_a7_base     (apb_a7_base+0x0000)
#define a7_rep_base      (apb_a7_base+0x2000)
#define a7_pmu_base      (apb_a7_base+0x3000)

#define sysctl_base      (apb_shr_base+0x0000)
#define fgpio_base       (apb_shr_base+0x1000)
#define hif_apb_base     (apb_shr_base+0x2000)
#define iodma_base       (apb_shr_base+0x3000)
#define memdma_base      (apb_shr_base+0x3800)
#define xfm_apb_base     (apb_shr_base+0x4000)
#define xsm_apb_base     (apb_shr_base+0x5000)
#define mis_apb_base     (apb_shr_base+0xf000)

#define sgpio_base       (apb_ayc_base+0x2000)
#define usbip_base       (apb_ayc_base+0x7000)

#define UART1_BASE       (APB_DMA_BASE+0x0000)
#define UART2_BASE       (APB_DMA_BASE+0x1000)
#define UART3_BASE       (APB_DMA_BASE+0x2000)
#define usbwrp_base      (apb_dma_base+0x3000)

#define XTAPBPBase	0x41002000
#define XTAHBMBase      0x41003000

/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
/* Howard						                     */
/***************************************************************************************************************************************************/
/***************************************************************************************************************************************************/
#define CPUSRAM3_END      0x30040000
#define CPUSRAM2_END      0x30030000
#define SDRAM_SOME        0x60050000
#define	dma_wait	*((volatile unsigned int *) (CPUSRAM3_END-0x4))  //(0x3001FFFC)) //0x0FF017FC)
#define	not_pass	*((volatile unsigned int *) (CPUSRAM3_END-0x8))  //(0x3001FFF8))
#define	proc_count	*((volatile unsigned int *) (CPUSRAM3_END-0x10)) //(0x3001FFF0))
#define	cpu_wait	*((volatile unsigned int *) (CPUSRAM3_END-0x14)) //(0x3001FFEC))
#define	sar_finish	*((volatile unsigned int *) (CPUSRAM3_END-0x18)) //(0x3001FFE8))
#define	RD_DATA_REG	*((volatile unsigned int *) (CPUSRAM3_END-0x20)) //(0x3001FFE0))
//#define	pass_count	*((volatile unsigned int *) (CPUSRAM3_END-0x24)) //(0x3001FFDC))
//#define	pass_count	*((volatile unsigned int *) (CPUSRAM3_END-0x28)) //(0x3001FFD8))
//#define	pass_count	*((volatile unsigned int *) (CPUSRAM3_END-0x2C)) //(0x3001FFD4))
#define	pass_count	*((volatile unsigned int *) (CPUSRAM3_END-0x30)) //(0x3001FFD0))
#define	pass_count_sdr	*((volatile unsigned int *) (SDRAM_SOME-0x0)) //(0x3001FFDC))

#define	RX_DATA1	*((volatile unsigned int *) (CPUSRAM2_END-0x4))   //(0x30017FFC))
#define	RX_DATA2	*((volatile unsigned int *) (CPUSRAM2_END-0x8))   //(0x30017FF8))
#define	RX_DATA3	*((volatile unsigned int *) (CPUSRAM2_END-0xC))   //(0x30017FF4))
#define	RX_DATA4	*((volatile unsigned int *) (CPUSRAM2_END-0x10))  //(0x30017FF0))


#define cpu_sram_2_base_1  0x30020100
#define cpu_sram_2_base_2  0x30020200
#define cpu_sram_2_base_3  0x30020300
#define cpu_sram_2_base_4  0x30020400
#define cpu_sram_2_base_5  0x30020500
#define cpu_sram_2_base_6  0x30020600
#define cpu_sram_2_base_7  0x30020700
#define cpu_sram_2_base_8  0x30020800
#define cpu_sram_2_base_9  0x30020900

#define CPUSRAM11Base  	(CPUSRAM1Base+0x1000)//0x30011000
#define CPUSRAM22Base  	(CPUSRAM2Base+0x0200)//0x30020200

  #define	cpu_sram_2_base_1_p	(volatile unsigned int  *) cpu_sram_2_base_1

#define USBDMABase         0x42003000


#define	sdram_addr_1 0x60AAA350
#define	sdram_addr_2 0x60765480
#define	sdram_addr_3 0x60123450
#define	sdram_addr_4 0x60001110
#define	sdram_addr_5 0x60030110
#define	sdram_addr_6 0x6000E550

  #define	sdram_addr_1_p	(volatile unsigned int  *) sdram_addr_1
  #define	sdram_addr_2_p	(volatile unsigned int  *) sdram_addr_2
  #define	sdram_addr_3_p	(volatile unsigned int  *) sdram_addr_3
  #define	sdram_addr_4_p	(volatile unsigned int  *) sdram_addr_4
  #define	sdram_addr_5_p	(volatile unsigned int  *) sdram_addr_5
  #define	sdram_addr_6_p	(volatile unsigned int  *) sdram_addr_6

#define InSramAdd00_3 ((volatile unsigned int *) (CPUSRAM3Base+0x000))
#define InSramAdd01_3 ((volatile unsigned int *) (CPUSRAM3Base+0x004))
#define InSramAdd02_3 ((volatile unsigned int *) (CPUSRAM3Base+0x008))
#define InSramAdd03_3 ((volatile unsigned int *) (CPUSRAM3Base+0x00C))
#define InSramAdd04_3 ((volatile unsigned int *) (CPUSRAM3Base+0x010))
#define InSramAdd05_3 ((volatile unsigned int *) (CPUSRAM3Base+0x014))
#define InSramAdd06_3 ((volatile unsigned int *) (CPUSRAM3Base+0x018))
#define InSramAdd07_3 ((volatile unsigned int *) (CPUSRAM3Base+0x01C))
#define InSramAdd08_3 ((volatile unsigned int *) (CPUSRAM3Base+0x020))
#define InSramAdd09_3 ((volatile unsigned int *) (CPUSRAM3Base+0x024))
#define InSramAdd10_3 ((volatile unsigned int *) (CPUSRAM3Base+0x028))
#define InSramAdd11_3 ((volatile unsigned int *) (CPUSRAM3Base+0x02C))
#define InSramAdd12_3 ((volatile unsigned int *) (CPUSRAM3Base+0x030))
#define InSramAdd13_3 ((volatile unsigned int *) (CPUSRAM3Base+0x034))
#define InSramAdd14_3 ((volatile unsigned int *) (CPUSRAM3Base+0x038))
#define InSramAdd15_3 ((volatile unsigned int *) (CPUSRAM3Base+0x03C))
#define InSramAdd16_3 ((volatile unsigned int *) (CPUSRAM3Base+0x040))
#define InSramAdd17_3 ((volatile unsigned int *) (CPUSRAM3Base+0x044))
#define InSramAdd18_3 ((volatile unsigned int *) (CPUSRAM3Base+0x048))
#define InSramAdd19_3 ((volatile unsigned int *) (CPUSRAM3Base+0x04C))
#define InSramAdd20_3 ((volatile unsigned int *) (CPUSRAM3Base+0x050))
#define InSramAdd21_3 ((volatile unsigned int *) (CPUSRAM3Base+0x054))
#define InSramAdd22_3 ((volatile unsigned int *) (CPUSRAM3Base+0x058))
#define InSramAdd23_3 ((volatile unsigned int *) (CPUSRAM3Base+0x05C))
#define InSramAdd24_3 ((volatile unsigned int *) (CPUSRAM3Base+0x060))
#define InSramAdd25_3 ((volatile unsigned int *) (CPUSRAM3Base+0x064))
#define InSramAdd26_3 ((volatile unsigned int *) (CPUSRAM3Base+0x068))
#define InSramAdd27_3 ((volatile unsigned int *) (CPUSRAM3Base+0x06C))

#define InSramAdd00_2 ((volatile unsigned int *) (CPUSRAM2Base+0x000))
#define InSramAdd01_2 ((volatile unsigned int *) (CPUSRAM2Base+0x004))
#define InSramAdd02_2 ((volatile unsigned int *) (CPUSRAM2Base+0x008))
#define InSramAdd03_2 ((volatile unsigned int *) (CPUSRAM2Base+0x00C))
#define InSramAdd04_2 ((volatile unsigned int *) (CPUSRAM2Base+0x010))
#define InSramAdd05_2 ((volatile unsigned int *) (CPUSRAM2Base+0x014))
#define InSramAdd06_2 ((volatile unsigned int *) (CPUSRAM2Base+0x018))
#define InSramAdd07_2 ((volatile unsigned int *) (CPUSRAM2Base+0x01C))
#define InSramAdd08_2 ((volatile unsigned int *) (CPUSRAM2Base+0x020))
#define InSramAdd09_2 ((volatile unsigned int *) (CPUSRAM2Base+0x024))
#define InSramAdd10_2 ((volatile unsigned int *) (CPUSRAM2Base+0x028))
#define InSramAdd11_2 ((volatile unsigned int *) (CPUSRAM2Base+0x02C))

#define InSramAdd0_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x000)) 
#define InSramAdd1_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x004)) 
#define InSramAdd2_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x008)) 
#define InSramAdd3_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x00C)) 
#define InSramAdd4_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x010)) 
#define InSramAdd5_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x014)) 
#define InSramAdd6_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x018)) 
#define InSramAdd7_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x01C)) 
#define InSramAdd8_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x020)) 
#define InSramAdd9_2   ((volatile unsigned int *) (CPUSRAM2Base+0x200+0x024)) 

#define InSramAdd_gea0 ((volatile unsigned int *) (CPUSRAM22Base+0x000)) 
#define InSramAdd_gea1 ((volatile unsigned int *) (CPUSRAM22Base+0x004)) 
#define InSramAdd_gea2 ((volatile unsigned int *) (CPUSRAM22Base+0x008)) 
#define InSramAdd_gea3 ((volatile unsigned int *) (CPUSRAM22Base+0x00C)) 
#define InSramAdd_gea4 ((volatile unsigned int *) (CPUSRAM22Base+0x010)) 
#define InSramAdd_gea5 ((volatile unsigned int *) (CPUSRAM22Base+0x014)) 
#define InSramAdd_gea6 ((volatile unsigned int *) (CPUSRAM22Base+0x018)) 
#define InSramAdd_gea7 ((volatile unsigned int *) (CPUSRAM22Base+0x01C)) 
#define InSramAdd_gea8 ((volatile unsigned int *) (CPUSRAM22Base+0x020)) 
#define InSramAdd_gea9 ((volatile unsigned int *) (CPUSRAM22Base+0x024)) 

/************************/
/* XFM priority setting */
/************************/
#define	A9I_PRI_1		  (unsigned int) 0x00000000
#define	COM_PRI_2		  (unsigned int) 0x00000018
#define	VDO_PRI_3		  (unsigned int) 0x00000100
#define	A9D_PRI_4		  (unsigned int) 0x00000200
#define	A7_PRI_5		  (unsigned int) 0x00002000



/************************/
/* USB physical meaning */
/************************/
#define	USB_RST_ITR_EN		  (unsigned int) 0x00000020
#define	USB_RST_ITR_CLR		  (unsigned int) 0x00000020
#define	USB_EN		          (unsigned int) 0x00000040
#define	USB_CONFIGURED	          (unsigned int) 0x00000002
#define	USB_SUS_ITR_EN		  (unsigned int) 0x00000010
#define	USB_SUS_ITR_CLR		  (unsigned int) 0x00000010
#define	USB_SUS_CTL_CLR		  (unsigned int) 0x00000001
#define	USB_FIFO_UnF_ITREN	  (unsigned int) 0x00000010
#define	USB_FIFO_OvF_ITREN	  (unsigned int) 0x00000020
#define	USB_DMAREQ_EN	          (unsigned int) 0x00000002