pll.c

realview下的一个arm9的bootloader烧录器.支持norflash读写

/******************************************************************************************************************
 *  DESCRIPTION: Switch PLL output frequency.
 *  Author:  Wen-Hung Wen
 *  Date: 2007/8/28
 *  Modification:
 *
 *  Status: 	PLL_id: Which PLL?
 * 			1: PLL1: its input source is master clock.
 *			2: PLL2: its input source is master clock.
 *			4: PLL4: its input source is PLL5.
 *			5: PLL5: its input source is master clock.
 *
 *			Frequency: Which frequency?
 *			   200:	201.5MHz to ARM9
 *				(201.5/2)MHz to ARM7
 *			   84:	84MHz to ARM9
 *				84MHz to ARM7
 *			   73:	73.125MHz to ARM9 
 *				73.125MHz to ARM7
 *		
 ******************************************************************************************************************/
#include "magic_reg_defs.h"
#include "pll.h"
#define input_26	0
#define input_pll5	1

/*
int main(void)
{
	//SwitchPLL(1,73);	
	//SwitchPLL(1,84);
	//SwitchPLL(1,200);
	//SwitchPLL(2,73);
	//SwitchPLL(2,84);
	//SwitchPLL(2,200);
	//SwitchPLL(5,73);
	//SwitchPLL(5,84);
	//SwitchPLL(5,200);
	//SwitchPLL(4,73);
	//SwitchPLL(4,84);
	//SwitchPLL(4,200);	
}
*/


int SwitchPLL1(int PLL_id, int Frequency)
{
	volatile unsigned int *cur_PLL_CTL_REG;
	//unsigned short divr = 3; 		//[4:0]
	//unsigned short divf = 0; 		//[7:0]
	//unsigned short divq = 3; 		//[2:0]	
	unsigned short source = input_26;

	//Select PATH
	/*
	*CKSW_REG &= ~(15<<20);		//ACLK/1(1)
	*CKSW_REG |= ~(1<<20);		//ACLK/1(2)
	*CKSW_REG &= ~(3);		//select PLL1, SW0 output as output.
	*CKSW_REG |= (0x1 << 2); 	//select SW1 output as output.
	*/
	
    	switch(PLL_id)
    	{
    		case 1:
    	    		cur_PLL_CTL_REG = PLL1_CTL_REG;	    		
    	    		break;
    		case 2:
    	    		cur_PLL_CTL_REG = PLL2_CTL_REG; 	    		    	    		
    	    		break;
    		case 4:
    	    		cur_PLL_CTL_REG = PLL4_CTL_REG;
    	    		source = input_pll5;
    	    		break;    		
    		case 5:
    	    		cur_PLL_CTL_REG = PLL5_CTL_REG;    	    		    	    			
    	    		break;    	    		
    		default:
    	    		//printf("Error: Unknow PLL\n");
    	    		return 0;
    	    		break;
    	}
    	
    	//1: Internal feedback
    	//*cur_PLL_CTL_REG |= PLL_FSEN;
		            		      
	//Non-reset and Not bypass
	//*cur_PLL_CTL_REG &= ~(3<<24);
    	
 	if( source == input_26)
 	{		 
	    	switch(Frequency)
	    	{
	    		case 73: 
				#define WITH_PLL
				#ifdef WITH_PLL
					*cur_PLL_CTL_REG = 0x00000001 + (0x2DL<<8) + (0x03L<<16) + (0x00400000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				#endif
					if(PLL_id==1)
					{
						*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
						//PLL1 or PLL2 can output frequency to clko pin "XCLK1".
						*CKSW2_REG |= (0x1 << 3);		//Turn on SW24 to output PLL.
						*CKSW2_REG |= (0x1 << 4);		//Select SW24 to clko.						
						//printf("Test PLL1 out freq=73.125MHz\r\n");
					}
					else if(PLL_id==2)
					{
						*CKSW2_REG |= (1<<5);	//CKSW26 selects D2;
						//PLL1 or PLL2 can output frequency to clko pin "XCLK1".
						*CKSW2_REG |= (0x1 << 3);		//Turn on SW24 to output PLL.
						*CKSW2_REG |= (0x1 << 4);		//Select SW24 to clko.							
						//printf("Test PLL2 out freq=84.5MHz\r\n");
					}
					else if(PLL_id==5)
					{
						//*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
						*CKSW_REG |= (1<<18);	//CKSW26 selects D2;
						
						//PLL4 or PLL5 can output frequency to clko pin "XCLK0".
						*CKSW_REG |= (0x1 << 16); 		//Turn on SW16 to output PLL.
						*CKSW_REG |= (0x1 << 17); 		//Select SW16 to clko.
						//printf("Test PLL5 out freq=73.125MHz\r\n");												
					}	
					//getchar(); 
					break;		
			case 84: 
				#define WITH_PLL
				#ifdef WITH_PLL
					*cur_PLL_CTL_REG = (0x0) + ( 12 << 8 ) + (0x2<<16) + PLL_RANGE42 + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR)) + HCLK_DIV_1;
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR | CKSW0_CLR | CKSW1_CLR | CKSW2_CLR)) + HCLK_DIV_1 + CKSW0_FR_PLL1 + CKSW1_FR_SW0 + CKSW2_FR_SW1;
				#endif	
					if(PLL_id==1)
					{
						*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
						//PLL1 or PLL2 can output frequency to clko pin "XCLK1".
						*CKSW2_REG |= (0x1 << 3);		//Turn on SW24 to output PLL.
						*CKSW2_REG |= (0x1 << 4);		//Select SW24 to clko.						
						//printf("Test PLL1 out freq=84.5MHz\r\n");
					}
					else if(PLL_id==2)
					{
						*CKSW2_REG |= (1<<5);	//CKSW26 selects D2;
						//PLL1 or PLL2 can output frequency to clko pin "XCLK1".
						*CKSW2_REG |= (0x1 << 3);		//Turn on SW24 to output PLL.
						*CKSW2_REG |= (0x1 << 4);		//Select SW24 to clko.							
						//printf("Test PLL2 out freq=84.5MHz\r\n");
					}
					else if(PLL_id==5)
					{
						//*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
						*CKSW_REG |= (1<<18);	//CKSW26 selects D2;
						
						//PLL4 or PLL5 can output frequency to clko pin "XCLK0".
						*CKSW_REG |= (0x1 << 16); 		//Turn on SW16 to output PLL.
						*CKSW_REG |= (0x1 << 17); 		//Select SW16 to clko.
						//printf("Test PLL5 out freq=84.5MHz\r\n");												
					}
					break;					
			case 200: 	
				//Test PLL1 out freq=201.5MHz*******************************************************************************************************
				
				#define WITH_PLL
				#ifdef WITH_PLL
					*cur_PLL_CTL_REG = 0x00000000 + (30<<8) + (2<<16) + (0x00700000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				#endif
				
				*CKSW_REG &= ~(0xF<<20); //Clear HCLK clock divider setting
				*CKSW_REG |= (2<<20); //ACKLK/2, ARM7 input freq = 201.5MHz/2
				
					if(PLL_id==1)
					{
						*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
						//PLL1 or PLL2 can output frequency to clko pin "XCLK1".
						*CKSW2_REG |= (0x1 << 3);		//Turn on SW24 to output PLL.
						*CKSW2_REG |= (0x1 << 4);		//Select SW24 to clko.						
						//printf("Test PLL1 out freq=201.5MHz\r\n");
					}
					else if(PLL_id==2)
					{
						*CKSW2_REG |= (1<<5);	//CKSW26 selects D2;
						//PLL1 or PLL2 can output frequency to clko pin "XCLK1".
						*CKSW2_REG |= (0x1 << 3);		//Turn on SW24 to output PLL.
						*CKSW2_REG |= (0x1 << 4);		//Select SW24 to clko.							
						//printf("Test PLL2 out freq=201.5MHz\r\n");
					}
					else if(PLL_id==5)
					{
						//*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
						*CKSW_REG |= (1<<18);	//CKSW26 selects D2;
						
						//PLL4 or PLL5 can output frequency to clko pin "XCLK0".
						*CKSW_REG |= (0x1 << 16); 		//Turn on SW16 to output PLL.
						*CKSW_REG |= (0x1 << 17); 		//Select SW16 to clko.
						//printf("Test PLL5 out freq=201.5MHz\r\n");												
					}
					break;											    			
	    		default:
	    			//printf("Error: Unknow frequency for PLL\n");
	    			break;
	    	}
	}
	else
	{	
	    	switch(Frequency)
	    	{
	    		case 73: 
				#define WITH_PLL
				#ifdef WITH_PLL
					*PLL5_CTL_REG = 0x00000001 + (0x2DL<<8) + (0x03L<<16) + (0x00400000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*PLL5_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				#endif
				#ifdef WITH_PLL
					*cur_PLL_CTL_REG = 0x00000000 + (0x7<<8) + (0x03<<16) + (0x00600000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR)) + HCLK_DIV_1;
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR | CKSW0_CLR | CKSW1_CLR | CKSW2_CLR)) + HCLK_DIV_1 + CKSW0_FR_PLL1 + CKSW1_FR_SW0 + CKSW2_FR_SW1;
				#endif			

				*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
												
				//PLL4 or PLL5 can output frequency to clko pin "XCLK0".
				*CKSW_REG |= (0x1 << 16); 		//Turn on SW16 to output PLL.
				*CKSW_REG |= (0x1 << 17); 		//Select SW16 to clko.
				//printf("Test PLL4 out freq=73.125MHz\r\n");												
						
				//getchar(); 
				break;		
			case 84: 
				#define WITH_PLL
				#ifdef WITH_PLL
					*PLL5_CTL_REG = (0x0) + ( 12 << 8 ) + (0x2<<16) + PLL_RANGE42 + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*PLL5_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				
					*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR)) + HCLK_DIV_1;
					*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR | CKSW0_CLR | CKSW1_CLR | CKSW2_CLR)) + HCLK_DIV_1 + CKSW0_FR_PLL1 + CKSW1_FR_SW0 + CKSW2_FR_SW1;
				#endif	
				#ifdef WITH_PLL
					*cur_PLL_CTL_REG = 0x00000000 + (0x7<<8) + (0x03<<16) + (0x00600000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR)) + HCLK_DIV_1;
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR | CKSW0_CLR | CKSW1_CLR | CKSW2_CLR)) + HCLK_DIV_1 + CKSW0_FR_PLL1 + CKSW1_FR_SW0 + CKSW2_FR_SW1;
				#endif					

				*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
												
						//PLL4 or PLL5 can output frequency to clko pin "XCLK0".
				*CKSW_REG |= (0x1 << 16); 		//Turn on SW16 to output PLL.
				*CKSW_REG |= (0x1 << 17); 		//Select SW16 to clko.
				//printf("Test PLL4 out freq=84.5MHz\r\n");												
						
				//getchar(); 
				break;					
			case 200: 	
				//Test PLL1 out freq=201.5MHz*******************************************************************************************************
				
				#define WITH_PLL
				#ifdef WITH_PLL
					*PLL5_CTL_REG = 0x00000000 + (30<<8) + (2<<16) + (0x00700000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*PLL5_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				#endif
				#ifdef WITH_PLL
					*cur_PLL_CTL_REG = 0x00000000 + (0x7<<8) + (0x03<<16) + (0x00600000) + PLL_FSEN + PLL_NO_RESET + PLL_NO_BYPAS;
					while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA)
					{
					}
				
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR)) + HCLK_DIV_1;
					//*CKSW_REG     = (*CKSW_REG & ~(HCLK_DIV_CLR | CKSW0_CLR | CKSW1_CLR | CKSW2_CLR)) + HCLK_DIV_1 + CKSW0_FR_PLL1 + CKSW1_FR_SW0 + CKSW2_FR_SW1;
				#endif					
				
				//*CKSW_REG |= (2<<20); //ACKLK/2, ARM7 input freq = 201.5MHz/2
				
				*CKSW2_REG &= ~(1<<5);	//CKSW26 selects D1;
												
						//PLL4 or PLL5 can output frequency to clko pin "XCLK0".
				*CKSW_REG |= (0x1 << 16); 		//Turn on SW16 to output PLL.
				*CKSW_REG |= (0x1 << 17); 		//Select SW16 to clko.
				//printf("Test PLL4 out freq=201.5MHz\r\n");												
						
				//getchar(); 
				break;											    			
	    		default:
	    			//printf("Error: Unknow frequency for PLL\n");
	    			break;
	    	}
	    				
	}
	
	//Wait for PLL is lock in
	while ((*cur_PLL_CTL_REG & PLL_LOCK_INDCA) != PLL_LOCK_INDCA );	
	return 1;
}


int pll_cksw_set(UINT32 PLL_id, UINT32 destination_id)
{
    int ret_val = -1;
    
    switch(destination_id)
    {
        case PLL_DST_MCU:
            switch(PLL_id)
            {
                case PLL_ID_1:
                    *CKSW_REG |= (0x1 << 2); /* CKSW2=1 sets HCLK = SW1 ( SW1=SW0, SW1=PLL1 ) */
                    ret_val = 1;
                    break;
                default:
                    break;
            }
            break;
            
        case PLL_DST_DSP:
            break;
            
        case PLL_DST_USB:
            break;
            
        case PLL_DST_RTC:
            break;
            
        case PLL_DST_32K_LOGIC:
            break;
            
    }

    return ret_val;    
}