psp.tan.qmsg

psp屏显示驱动程序cpld veriloghdl

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "WR register WADDER\[17\] register WADDER\[9\] 3.408 ns " "Info: Minimum slack time is 3.408 ns for clock \"WR\" between source register \"WADDER\[17\]\" and destination register \"WADDER\[9\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.253 ns + Shortest register register " "Info: + Shortest register to register delay is 3.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns WADDER\[17\] 1 REG LC_X9_Y6_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N9; Fanout = 4; REG Node = 'WADDER\[17\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WADDER[17] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.511 ns) 1.896 ns Equal1~204 2 COMB LC_X8_Y6_N8 11 " "Info: 2: + IC(1.385 ns) + CELL(0.511 ns) = 1.896 ns; Loc. = LC_X8_Y6_N8; Fanout = 11; COMB Node = 'Equal1~204'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.896 ns" { WADDER[17] Equal1~204 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 234 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.591 ns) 3.253 ns WADDER\[9\] 3 REG LC_X8_Y6_N1 5 " "Info: 3: + IC(0.766 ns) + CELL(0.591 ns) = 3.253 ns; Loc. = LC_X8_Y6_N1; Fanout = 5; REG Node = 'WADDER\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.357 ns" { Equal1~204 WADDER[9] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.102 ns ( 33.88 % ) " "Info: Total cell delay = 1.102 ns ( 33.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.151 ns ( 66.12 % ) " "Info: Total interconnect delay = 2.151 ns ( 66.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.253 ns" { WADDER[17] Equal1~204 WADDER[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.253 ns" { WADDER[17] Equal1~204 WADDER[9] } { 0.000ns 1.385ns 0.766ns } { 0.000ns 0.511ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.155 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.155 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 9.259 ns " "Info: + Latch edge is 9.259 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WR 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Destination clock \"WR\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 9.259 ns " "Info: - Launch edge is 9.259 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WR 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Source clock \"WR\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 7.143 ns + Longest register " "Info: + Longest clock path from clock \"WR\" to destination register is 7.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_61 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 34; CLK Node = 'WR'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.093 ns) + CELL(0.918 ns) 7.143 ns WADDER\[9\] 2 REG LC_X8_Y6_N1 5 " "Info: 2: + IC(5.093 ns) + CELL(0.918 ns) = 7.143 ns; Loc. = LC_X8_Y6_N1; Fanout = 5; REG Node = 'WADDER\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.011 ns" { WR WADDER[9] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 28.70 % ) " "Info: Total cell delay = 2.050 ns ( 28.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.093 ns ( 71.30 % ) " "Info: Total interconnect delay = 5.093 ns ( 71.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR source 7.143 ns - Shortest register " "Info: - Shortest clock path from clock \"WR\" to source register is 7.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_61 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 34; CLK Node = 'WR'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.093 ns) + CELL(0.918 ns) 7.143 ns WADDER\[17\] 2 REG LC_X9_Y6_N9 4 " "Info: 2: + IC(5.093 ns) + CELL(0.918 ns) = 7.143 ns; Loc. = LC_X9_Y6_N9; Fanout = 4; REG Node = 'WADDER\[17\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.011 ns" { WR WADDER[17] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 28.70 % ) " "Info: Total cell delay = 2.050 ns ( 28.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.093 ns ( 71.30 % ) " "Info: Total interconnect delay = 5.093 ns ( 71.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[17] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[17] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[17] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.253 ns" { WADDER[17] Equal1~204 WADDER[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.253 ns" { WADDER[17] Equal1~204 WADDER[9] } { 0.000ns 1.385ns 0.766ns } { 0.000ns 0.511ns 0.591ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[17] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "RamB0\[12\] RamData\[12\] clk 4.542 ns register " "Info: tsu for register \"RamB0\[12\]\" (data pin = \"RamData\[12\]\", clock pin = \"clk\") is 4.542 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.890 ns + Longest pin register " "Info: + Longest pin to register delay is 7.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RamData\[12\] 1 PIN PIN_109 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_109; Fanout = 1; PIN Node = 'RamData\[12\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[12] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns RamData\[12\]~19 2 COMB IOC_X12_Y8_N1 6 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X12_Y8_N1; Fanout = 6; COMB Node = 'RamData\[12\]~19'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { RamData[12] RamData[12]~19 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.167 ns) + CELL(0.591 ns) 7.890 ns RamB0\[12\] 3 REG LC_X3_Y7_N0 1 " "Info: 3: + IC(6.167 ns) + CELL(0.591 ns) = 7.890 ns; Loc. = LC_X3_Y7_N0; Fanout = 1; REG Node = 'RamB0\[12\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.758 ns" { RamData[12]~19 RamB0[12] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 21.84 % ) " "Info: Total cell delay = 1.723 ns ( 21.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.167 ns ( 78.16 % ) " "Info: Total interconnect delay = 6.167 ns ( 78.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.890 ns" { RamData[12] RamData[12]~19 RamB0[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.890 ns" { RamData[12] RamData[12]~19 RamB0[12] } { 0.000ns 0.000ns 6.167ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 187 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 187; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout =