📄 psp.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "WR register WADDER\[5\] register wridata\[9\] 4.426 ns " "Info: Slack time is 4.426 ns for clock \"WR\" between source register \"WADDER\[5\]\" and destination register \"wridata\[9\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "70.96 MHz 14.092 ns " "Info: Fmax is 70.96 MHz (period= 14.092 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "17.809 ns + Largest register register " "Info: + Largest register to register requirement is 17.809 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "18.518 ns + " "Info: + Setup relationship between source and destination is 18.518 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 27.777 ns " "Info: + Latch edge is 27.777 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WR 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Destination clock \"WR\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 9.259 ns " "Info: - Launch edge is 9.259 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WR 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Source clock \"WR\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 7.143 ns + Shortest register " "Info: + Shortest clock path from clock \"WR\" to destination register is 7.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_61 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 34; CLK Node = 'WR'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.093 ns) + CELL(0.918 ns) 7.143 ns wridata\[9\] 2 REG LC_X7_Y6_N6 1 " "Info: 2: + IC(5.093 ns) + CELL(0.918 ns) = 7.143 ns; Loc. = LC_X7_Y6_N6; Fanout = 1; REG Node = 'wridata\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.011 ns" { WR wridata[9] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 28.70 % ) " "Info: Total cell delay = 2.050 ns ( 28.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.093 ns ( 71.30 % ) " "Info: Total interconnect delay = 5.093 ns ( 71.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR wridata[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout wridata[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR source 7.143 ns - Longest register " "Info: - Longest clock path from clock \"WR\" to source register is 7.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_61 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 34; CLK Node = 'WR'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.093 ns) + CELL(0.918 ns) 7.143 ns WADDER\[5\] 2 REG LC_X7_Y5_N6 5 " "Info: 2: + IC(5.093 ns) + CELL(0.918 ns) = 7.143 ns; Loc. = LC_X7_Y5_N6; Fanout = 5; REG Node = 'WADDER\[5\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.011 ns" { WR WADDER[5] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 28.70 % ) " "Info: Total cell delay = 2.050 ns ( 28.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.093 ns ( 71.30 % ) " "Info: Total interconnect delay = 5.093 ns ( 71.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[5] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR wridata[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout wridata[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[5] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR wridata[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout wridata[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[5] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.383 ns - Longest register register " "Info: - Longest register to register delay is 13.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns WADDER\[5\] 1 REG LC_X7_Y5_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y5_N6; Fanout = 5; REG Node = 'WADDER\[5\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WADDER[5] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.881 ns) + CELL(0.747 ns) 2.628 ns Add3~321 2 COMB LC_X7_Y4_N6 2 " "Info: 2: + IC(1.881 ns) + CELL(0.747 ns) = 2.628 ns; Loc. = LC_X7_Y4_N6; Fanout = 2; COMB Node = 'Add3~321'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.628 ns" { WADDER[5] Add3~321 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.751 ns Add3~323 3 COMB LC_X7_Y4_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.751 ns; Loc. = LC_X7_Y4_N7; Fanout = 2; COMB Node = 'Add3~323'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add3~321 Add3~323 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.874 ns Add3~325 4 COMB LC_X7_Y4_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.874 ns; Loc. = LC_X7_Y4_N8; Fanout = 2; COMB Node = 'Add3~325'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add3~323 Add3~325 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 3.689 ns Add3~326 5 COMB LC_X7_Y4_N9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.815 ns) = 3.689 ns; Loc. = LC_X7_Y4_N9; Fanout = 2; COMB Node = 'Add3~326'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add3~325 Add3~326 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 239 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.889 ns) + CELL(0.511 ns) 6.089 ns wridata\[0\]~895 6 COMB LC_X8_Y4_N9 1 " "Info: 6: + IC(1.889 ns) + CELL(0.511 ns) = 6.089 ns; Loc. = LC_X8_Y4_N9; Fanout = 1; COMB Node = 'wridata\[0\]~895'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { Add3~326 wridata[0]~895 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.914 ns) 8.121 ns wridata\[0\]~897 7 COMB LC_X9_Y4_N3 1 " "Info: 7: + IC(1.118 ns) + CELL(0.914 ns) = 8.121 ns; Loc. = LC_X9_Y4_N3; Fanout = 1; COMB Node = 'wridata\[0\]~897'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { wridata[0]~895 wridata[0]~897 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.200 ns) 9.045 ns wridata\[0\]~899 8 COMB LC_X9_Y4_N5 1 " "Info: 8: + IC(0.724 ns) + CELL(0.200 ns) = 9.045 ns; Loc. = LC_X9_Y4_N5; Fanout = 1; COMB Node = 'wridata\[0\]~899'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.924 ns" { wridata[0]~897 wridata[0]~899 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 9.550 ns wridata\[0\]~900 9 COMB LC_X9_Y4_N6 16 " "Info: 9: + IC(0.305 ns) + CELL(0.200 ns) = 9.550 ns; Loc. = LC_X9_Y4_N6; Fanout = 16; COMB Node = 'wridata\[0\]~900'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { wridata[0]~899 wridata[0]~900 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.590 ns) + CELL(1.243 ns) 13.383 ns wridata\[9\] 10 REG LC_X7_Y6_N6 1 " "Info: 10: + IC(2.590 ns) + CELL(1.243 ns) = 13.383 ns; Loc. = LC_X7_Y6_N6; Fanout = 1; REG Node = 'wridata\[9\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.833 ns" { wridata[0]~900 wridata[9] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 229 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.876 ns ( 36.43 % ) " "Info: Total cell delay = 4.876 ns ( 36.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.507 ns ( 63.57 % ) " "Info: Total interconnect delay = 8.507 ns ( 63.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { WADDER[5] Add3~321 Add3~323 Add3~325 Add3~326 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { WADDER[5] Add3~321 Add3~323 Add3~325 Add3~326 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[9] } { 0.000ns 1.881ns 0.000ns 0.000ns 0.000ns 1.889ns 1.118ns 0.724ns 0.305ns 2.590ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.815ns 0.511ns 0.914ns 0.200ns 0.200ns 1.243ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR wridata[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout wridata[9] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { WR WADDER[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.143 ns" { WR WR~combout WADDER[5] } { 0.000ns 0.000ns 5.093ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { WADDER[5] Add3~321 Add3~323 Add3~325 Add3~326 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { WADDER[5] Add3~321 Add3~323 Add3~325 Add3~326 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[9] } { 0.000ns 1.881ns 0.000ns 0.000ns 0.000ns 1.889ns 1.118ns 0.724ns 0.305ns 2.590ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.815ns 0.511ns 0.914ns 0.200ns 0.200ns 1.243ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register RamB0\[2\] register pspdata\[18\]~reg0 -2.556 ns " "Info: Minimum slack time is -2.556 ns for clock \"clk\" between source register \"RamB0\[2\]\" and destination register \"pspdata\[18\]~reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.491 ns + Shortest register register " "Info: + Shortest register to register delay is 1.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RamB0\[2\] 1 REG LC_X4_Y5_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y5_N2; Fanout = 1; REG Node = 'RamB0\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamB0[2] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns Selector28~13 2 COMB LC_X4_Y5_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X4_Y5_N2; Fanout = 1; COMB Node = 'Selector28~13'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { RamB0[2] Selector28~13 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 279 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 1.491 ns pspdata\[18\]~reg0 3 REG LC_X4_Y5_N3 1 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 1.491 ns; Loc. = LC_X4_Y5_N3; Fanout = 1; REG Node = 'pspdata\[18\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { Selector28~13 pspdata[18]~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.186 ns ( 79.54 % ) " "Info: Total cell delay = 1.186 ns ( 79.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.305 ns ( 20.46 % ) " "Info: Total interconnect delay = 0.305 ns ( 20.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { RamB0[2] Selector28~13 pspdata[18]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.491 ns" { RamB0[2] Selector28~13 pspdata[18]~reg0 } { 0.000ns 0.000ns 0.305ns } { 0.000ns 0.595ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.047 ns - Smallest register register " "Info: - Smallest register to register requirement is 4.047 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 18.518 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 18.518 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 18.518 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 18.518 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.202 ns + Smallest " "Info: + Smallest clock skew is 4.202 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.883 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 187 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 187; CLK Node = 'clk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns pspclk~reg0 2 REG LC_X10_Y3_N3 43 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X10_Y3_N3; Fanout = 43; REG Node = 'pspclk~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk pspclk~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 61 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.908 ns) + CELL(0.918 ns) 7.883 ns pspdata\[18\]~reg0 3 REG LC_X4_Y5_N3 1 " "Info: 3: + IC(2.908 ns) + CELL(0.918 ns) = 7.883 ns; Loc. = LC_X4_Y5_N3; Fanout = 1; REG Node = 'pspdata\[18\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.826 ns" { pspclk~reg0 pspdata[18]~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.81 % ) " "Info: Total cell delay = 3.375 ns ( 42.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.508 ns ( 57.19 % ) " "Info: Total interconnect delay = 4.508 ns ( 57.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { clk pspclk~reg0 pspdata[18]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { clk clk~combout pspclk~reg0 pspdata[18]~reg0 } { 0.000ns 0.000ns 1.600ns 2.908ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 187 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 187; CLK Node = 'clk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns RamB0\[2\] 2 REG LC_X4_Y5_N2 1 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X4_Y5_N2; Fanout = 1; REG Node = 'RamB0\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk RamB0[2] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamB0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamB0[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { clk pspclk~reg0 pspdata[18]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { clk clk~combout pspclk~reg0 pspdata[18]~reg0 } { 0.000ns 0.000ns 1.600ns 2.908ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamB0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamB0[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { clk pspclk~reg0 pspdata[18]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { clk clk~combout pspclk~reg0 pspdata[18]~reg0 } { 0.000ns 0.000ns 1.600ns 2.908ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamB0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamB0[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { RamB0[2] Selector28~13 pspdata[18]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.491 ns" { RamB0[2] Selector28~13 pspdata[18]~reg0 } { 0.000ns 0.000ns 0.305ns } { 0.000ns 0.595ns 0.591ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { clk pspclk~reg0 pspdata[18]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { clk clk~combout pspclk~reg0 pspdata[18]~reg0 } { 0.000ns 0.000ns 1.600ns 2.908ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamB0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamB0[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "clk 84 " "Warning: Can't achieve minimum setup and hold requirement clk along 84 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
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