psp.tan.qmsg

psp屏显示驱动程序cpld veriloghdl

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VS~reg0 " "Info: Detected ripple clock \"VS~reg0\" as buffer" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 317 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VS~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "pspclk~reg0 " "Info: Detected ripple clock \"pspclk~reg0\" as buffer" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 61 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspclk~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "HS~reg0 " "Info: Detected ripple clock \"HS~reg0\" as buffer" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HS~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register addstart register RADDER\[8\] -4.219 ns " "Info: Slack time is -4.219 ns for clock \"clk\" between source register \"addstart\" and destination register \"RADDER\[8\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "37.1 MHz 26.956 ns " "Info: Fmax is 37.1 MHz (period= 26.956 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.353 ns + Largest register register " "Info: + Largest register to register requirement is -0.353 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "9.259 ns + " "Info: + Setup relationship between source and destination is 9.259 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 18.518 ns " "Info: + Latch edge is 18.518 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 18.518 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 18.518 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 9.259 ns " "Info: - Launch edge is 9.259 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Source clock \"clk\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.903 ns + Largest " "Info: + Largest clock skew is -8.903 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 187 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 187; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns RADDER\[8\] 2 REG LC_X8_Y5_N9 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y5_N9; Fanout = 3; REG Node = 'RADDER\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk RADDER[8] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RADDER[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RADDER[8] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.584 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 187 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 187; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns pspclk~reg0 2 REG LC_X10_Y3_N3 43 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X10_Y3_N3; Fanout = 43; REG Node = 'pspclk~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk pspclk~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 61 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.908 ns) + CELL(1.294 ns) 8.259 ns HS~reg0 3 REG LC_X11_Y3_N6 14 " "Info: 3: + IC(2.908 ns) + CELL(1.294 ns) = 8.259 ns; Loc. = LC_X11_Y3_N6; Fanout = 14; REG Node = 'HS~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { pspclk~reg0 HS~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.407 ns) + CELL(0.918 ns) 12.584 ns addstart 4 REG LC_X10_Y5_N7 3 " "Info: 4: + IC(3.407 ns) + CELL(0.918 ns) = 12.584 ns; Loc. = LC_X10_Y5_N7; Fanout = 3; REG Node = 'addstart'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.325 ns" { HS~reg0 addstart } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 37.10 % ) " "Info: Total cell delay = 4.669 ns ( 37.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.915 ns ( 62.90 % ) " "Info: Total interconnect delay = 7.915 ns ( 62.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.584 ns" { clk pspclk~reg0 HS~reg0 addstart } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.584 ns" { clk clk~combout pspclk~reg0 HS~reg0 addstart } { 0.000ns 0.000ns 1.600ns 2.908ns 3.407ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RADDER[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RADDER[8] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.584 ns" { clk pspclk~reg0 HS~reg0 addstart } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.584 ns" { clk clk~combout pspclk~reg0 HS~reg0 addstart } { 0.000ns 0.000ns 1.600ns 2.908ns 3.407ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RADDER[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RADDER[8] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.584 ns" { clk pspclk~reg0 HS~reg0 addstart } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.584 ns" { clk clk~combout pspclk~reg0 HS~reg0 addstart } { 0.000ns 0.000ns 1.600ns 2.908ns 3.407ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.866 ns - Longest register register " "Info: - Longest register to register delay is 3.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addstart 1 REG LC_X10_Y5_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y5_N7; Fanout = 3; REG Node = 'addstart'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { addstart } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.328 ns) + CELL(0.200 ns) 1.528 ns RADDER\[0\]~258 2 COMB LC_X9_Y5_N9 18 " "Info: 2: + IC(1.328 ns) + CELL(0.200 ns) = 1.528 ns; Loc. = LC_X9_Y5_N9; Fanout = 18; COMB Node = 'RADDER\[0\]~258'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.528 ns" { addstart RADDER[0]~258 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(1.243 ns) 3.866 ns RADDER\[8\] 3 REG LC_X8_Y5_N9 3 " "Info: 3: + IC(1.095 ns) + CELL(1.243 ns) = 3.866 ns; Loc. = LC_X8_Y5_N9; Fanout = 3; REG Node = 'RADDER\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.338 ns" { RADDER[0]~258 RADDER[8] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.443 ns ( 37.33 % ) " "Info: Total cell delay = 1.443 ns ( 37.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.423 ns ( 62.67 % ) " "Info: Total interconnect delay = 2.423 ns ( 62.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.866 ns" { addstart RADDER[0]~258 RADDER[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.866 ns" { addstart RADDER[0]~258 RADDER[8] } { 0.000ns 1.328ns 1.095ns } { 0.000ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RADDER[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RADDER[8] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.584 ns" { clk pspclk~reg0 HS~reg0 addstart } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.584 ns" { clk clk~combout pspclk~reg0 HS~reg0 addstart } { 0.000ns 0.000ns 1.600ns 2.908ns 3.407ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.866 ns" { addstart RADDER[0]~258 RADDER[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.866 ns" { addstart RADDER[0]~258 RADDER[8] } { 0.000ns 1.328ns 1.095ns } { 0.000ns 0.200ns 1.243ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clk' 18 " "Warning: Can't achieve timing requirement Clock Setup: 'clk' along 18 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}