psp.fit.qmsg

psp屏显示驱动程序cpld veriloghdl

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:08 " "Info: Fitter placement operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.230 ns register register " "Info: Estimated most critical path is register to register delay of 4.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addstart 1 REG LAB_X10_Y5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y5; Fanout = 3; REG Node = 'addstart'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { addstart } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.511 ns) 1.782 ns RADDER\[0\]~258 2 COMB LAB_X9_Y5 18 " "Info: 2: + IC(1.271 ns) + CELL(0.511 ns) = 1.782 ns; Loc. = LAB_X9_Y5; Fanout = 18; COMB Node = 'RADDER\[0\]~258'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.782 ns" { addstart RADDER[0]~258 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.205 ns) + CELL(1.243 ns) 4.230 ns RADDER\[0\] 3 REG LAB_X8_Y5 4 " "Info: 3: + IC(1.205 ns) + CELL(1.243 ns) = 4.230 ns; Loc. = LAB_X8_Y5; Fanout = 4; REG Node = 'RADDER\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { RADDER[0]~258 RADDER[0] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.754 ns ( 41.47 % ) " "Info: Total cell delay = 1.754 ns ( 41.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.476 ns ( 58.53 % ) " "Info: Total interconnect delay = 2.476 ns ( 58.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.230 ns" { addstart RADDER[0]~258 RADDER[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_VERY_HIGH_HOLD_REQUIREMENTS_DETECTED" "10 1055 " "Warning: 10 (of 1055) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." { { "Info" "IFITAPI_FITAPI_INFO_VPR_REGISTERS_WITH_VERY_HIGH_HOLD_REQUIREMENTS" "10 " "Info: Found 10 Registers with very high hold time requirements" { { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "pspdataChoose.011 " "Info: Node \"pspdataChoose.011\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "pspdataChoose.011 " "Info: Registered output is \"pspdataChoose.011\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdataChoose.011" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdataChoose.011 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdataChoose.011 } "NODE_NAME" } }  } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "pspdata\[8\]~1042 " "Info: Combinational output is \"pspdata\[8\]~1042\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdataChoose.011" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdataChoose.011 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdataChoose.011 } "NODE_NAME" } }  } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0}  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdataChoose.011" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdataChoose.011 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdataChoose.011 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[0\]~reg0 " "Info: Node \"pspdata\[0\]~reg0\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[0\]~reg0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[0]~reg0 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[1\]~reg0 " "Info: Node \"pspdata\[1\]~reg0\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[1\]~reg0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[1]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[1]~reg0 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[8\]~reg0 " "Info: Node \"pspdata\[8\]~reg0\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[8\]~reg0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[8]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[8]~reg0 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[16\]~reg0 " "Info: Node \"pspdata\[16\]~reg0\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[16\]~reg0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[16]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[16]~reg0 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[17\]~reg0 " "Info: Node \"pspdata\[17\]~reg0\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[17\]~reg0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[17]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[17]~reg0 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[9\]~reg0 " "Info: Node \"pspdata\[9\]~reg0\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[9\]~reg0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[9]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[9]~reg0 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "J1\[7\] " "Info: Node \"J1\[7\]\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "J1\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { J1[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { J1[7] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "J1\[9\] " "Info: Node \"J1\[9\]\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "J1\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { J1[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { J1[9] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "pspdata\[12\]~en " "Info: Node \"pspdata\[12\]~en\"" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 255 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "pspdata\[12\]~en" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[12]~en } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pspdata[12]~en } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found %1!d! Registers with very high hold time requirements" 0 0 "" 0}  } {  } 0 0 "%1!d! (of %2!d!) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 19 " "Info: Average interconnect usage is 19% of the available device resources. Peak interconnect usage is 19%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X13_Y8 " "Info: The peak interconnect region extends from location X0_Y0 to location X13_Y8" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "BH GND " "Info: Pin BH has GND driving its datain port" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 5 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "BH" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BH } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BH } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "BL GND " "Info: Pin BL has GND driving its datain port" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 5 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "BL" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BL } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BL } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "oe " "Info: Following pins have the same output enable: oe" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[11\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[11\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[15\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[15\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[10\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[10\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[14\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[14\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[9\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[9\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[13\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[13\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[8\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[8\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional RamData\[12\] 3.3-V LVTTL " "Info: Type bidirectional pin RamData\[12\] uses the 3.3-V LVTTL I/O standard" {  } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "RamData\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamData[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/MYPSP测试程序/MYPSP/PSP.fit.smsg " "Info: Generated suppressed messages file D:/MYPSP测试程序/MYPSP/PSP.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 01 21:13:19 2007 " "Info: Processing ended: Sat Dec 01 21:13:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Info: Elapsed time: 00:00:31" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}