📄 prev_cmp_psp.tan.qmsg
字号:
{ "Info" "ITDB_FULL_SLACK_RESULT" "WR register WADDER\[2\] register wridata\[15\] 4.856 ns " "Info: Slack time is 4.856 ns for clock \"WR\" between source register \"WADDER\[2\]\" and destination register \"wridata\[15\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "73.2 MHz 13.662 ns " "Info: Fmax is 73.2 MHz (period= 13.662 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "17.809 ns + Largest register register " "Info: + Largest register to register requirement is 17.809 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "18.518 ns + " "Info: + Setup relationship between source and destination is 18.518 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 27.777 ns " "Info: + Latch edge is 27.777 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WR 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Destination clock \"WR\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 9.259 ns " "Info: - Launch edge is 9.259 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WR 18.518 ns 9.259 ns inverted 50 " "Info: Clock period of Source clock \"WR\" is 18.518 ns with inverted offset of 9.259 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 7.028 ns + Shortest register " "Info: + Shortest clock path from clock \"WR\" to destination register is 7.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_61 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 34; CLK Node = 'WR'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.978 ns) + CELL(0.918 ns) 7.028 ns wridata\[15\] 2 REG LC_X6_Y7_N0 1 " "Info: 2: + IC(4.978 ns) + CELL(0.918 ns) = 7.028 ns; Loc. = LC_X6_Y7_N0; Fanout = 1; REG Node = 'wridata\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.896 ns" { WR wridata[15] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 29.17 % ) " "Info: Total cell delay = 2.050 ns ( 29.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.978 ns ( 70.83 % ) " "Info: Total interconnect delay = 4.978 ns ( 70.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR wridata[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout wridata[15] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR source 7.028 ns - Longest register " "Info: - Longest clock path from clock \"WR\" to source register is 7.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_61 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_61; Fanout = 34; CLK Node = 'WR'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.978 ns) + CELL(0.918 ns) 7.028 ns WADDER\[2\] 2 REG LC_X4_Y4_N9 5 " "Info: 2: + IC(4.978 ns) + CELL(0.918 ns) = 7.028 ns; Loc. = LC_X4_Y4_N9; Fanout = 5; REG Node = 'WADDER\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.896 ns" { WR WADDER[2] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 29.17 % ) " "Info: Total cell delay = 2.050 ns ( 29.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.978 ns ( 70.83 % ) " "Info: Total interconnect delay = 4.978 ns ( 70.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR WADDER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout WADDER[2] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR wridata[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout wridata[15] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR WADDER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout WADDER[2] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR wridata[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout wridata[15] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR WADDER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout WADDER[2] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.953 ns - Longest register register " "Info: - Longest register to register delay is 12.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns WADDER\[2\] 1 REG LC_X4_Y4_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N9; Fanout = 5; REG Node = 'WADDER\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WADDER[2] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.986 ns) + CELL(0.978 ns) 2.964 ns Add3~315 2 COMB LC_X5_Y4_N3 2 " "Info: 2: + IC(1.986 ns) + CELL(0.978 ns) = 2.964 ns; Loc. = LC_X5_Y4_N3; Fanout = 2; COMB Node = 'Add3~315'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.964 ns" { WADDER[2] Add3~315 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 274 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 3.225 ns Add3~317 3 COMB LC_X5_Y4_N4 6 " "Info: 3: + IC(0.000 ns) + CELL(0.261 ns) = 3.225 ns; Loc. = LC_X5_Y4_N4; Fanout = 6; COMB Node = 'Add3~317'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { Add3~315 Add3~317 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 274 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 4.200 ns Add3~324 4 COMB LC_X5_Y4_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.975 ns) = 4.200 ns; Loc. = LC_X5_Y4_N8; Fanout = 2; COMB Node = 'Add3~324'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { Add3~317 Add3~324 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 274 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.910 ns) + CELL(0.511 ns) 6.621 ns wridata\[0\]~895 5 COMB LC_X6_Y4_N9 1 " "Info: 5: + IC(1.910 ns) + CELL(0.511 ns) = 6.621 ns; Loc. = LC_X6_Y4_N9; Fanout = 1; COMB Node = 'wridata\[0\]~895'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.421 ns" { Add3~324 wridata[0]~895 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.742 ns) + CELL(0.511 ns) 8.874 ns wridata\[0\]~897 6 COMB LC_X7_Y4_N2 1 " "Info: 6: + IC(1.742 ns) + CELL(0.511 ns) = 8.874 ns; Loc. = LC_X7_Y4_N2; Fanout = 1; COMB Node = 'wridata\[0\]~897'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.253 ns" { wridata[0]~895 wridata[0]~897 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 9.379 ns wridata\[0\]~899 7 COMB LC_X7_Y4_N3 1 " "Info: 7: + IC(0.305 ns) + CELL(0.200 ns) = 9.379 ns; Loc. = LC_X7_Y4_N3; Fanout = 1; COMB Node = 'wridata\[0\]~899'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { wridata[0]~897 wridata[0]~899 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 9.884 ns wridata\[0\]~900 8 COMB LC_X7_Y4_N4 16 " "Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 9.884 ns; Loc. = LC_X7_Y4_N4; Fanout = 16; COMB Node = 'wridata\[0\]~900'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { wridata[0]~899 wridata[0]~900 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.826 ns) + CELL(1.243 ns) 12.953 ns wridata\[15\] 9 REG LC_X6_Y7_N0 1 " "Info: 9: + IC(1.826 ns) + CELL(1.243 ns) = 12.953 ns; Loc. = LC_X6_Y7_N0; Fanout = 1; REG Node = 'wridata\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { wridata[0]~900 wridata[15] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 264 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.879 ns ( 37.67 % ) " "Info: Total cell delay = 4.879 ns ( 37.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.074 ns ( 62.33 % ) " "Info: Total interconnect delay = 8.074 ns ( 62.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.953 ns" { WADDER[2] Add3~315 Add3~317 Add3~324 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.953 ns" { WADDER[2] Add3~315 Add3~317 Add3~324 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[15] } { 0.000ns 1.986ns 0.000ns 0.000ns 1.910ns 1.742ns 0.305ns 0.305ns 1.826ns } { 0.000ns 0.978ns 0.261ns 0.975ns 0.511ns 0.511ns 0.200ns 0.200ns 1.243ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR wridata[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout wridata[15] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.028 ns" { WR WADDER[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.028 ns" { WR WR~combout WADDER[2] } { 0.000ns 0.000ns 4.978ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.953 ns" { WADDER[2] Add3~315 Add3~317 Add3~324 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.953 ns" { WADDER[2] Add3~315 Add3~317 Add3~324 wridata[0]~895 wridata[0]~897 wridata[0]~899 wridata[0]~900 wridata[15] } { 0.000ns 1.986ns 0.000ns 0.000ns 1.910ns 1.742ns 0.305ns 0.305ns 1.826ns } { 0.000ns 0.978ns 0.261ns 0.975ns 0.511ns 0.511ns 0.200ns 0.200ns 1.243ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register RamC0\[6\] register pspdata\[6\]~reg0 -2.531 ns " "Info: Minimum slack time is -2.531 ns for clock \"clk\" between source register \"RamC0\[6\]\" and destination register \"pspdata\[6\]~reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.491 ns + Shortest register register " "Info: + Shortest register to register delay is 1.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RamC0\[6\] 1 REG LC_X10_Y7_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y7_N5; Fanout = 1; REG Node = 'RamC0\[6\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RamC0[6] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 95 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns Selector41~13 2 COMB LC_X10_Y7_N5 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X10_Y7_N5; Fanout = 1; COMB Node = 'Selector41~13'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { RamC0[6] Selector41~13 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 316 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 1.491 ns pspdata\[6\]~reg0 3 REG LC_X10_Y7_N6 1 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 1.491 ns; Loc. = LC_X10_Y7_N6; Fanout = 1; REG Node = 'pspdata\[6\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { Selector41~13 pspdata[6]~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 290 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.186 ns ( 79.54 % ) " "Info: Total cell delay = 1.186 ns ( 79.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.305 ns ( 20.46 % ) " "Info: Total interconnect delay = 0.305 ns ( 20.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { RamC0[6] Selector41~13 pspdata[6]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.491 ns" { RamC0[6] Selector41~13 pspdata[6]~reg0 } { 0.000ns 0.000ns 0.305ns } { 0.000ns 0.595ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.022 ns - Smallest register register " "Info: - Smallest register to register requirement is 4.022 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 18.518 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 18.518 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 18.518 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 18.518 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.177 ns + Smallest " "Info: + Smallest clock skew is 4.177 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.858 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 188 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 188; CLK Node = 'clk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns pspclk~reg0 2 REG LC_X10_Y3_N8 43 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X10_Y3_N8; Fanout = 43; REG Node = 'pspclk~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk pspclk~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 63 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.883 ns) + CELL(0.918 ns) 7.858 ns pspdata\[6\]~reg0 3 REG LC_X10_Y7_N6 1 " "Info: 3: + IC(2.883 ns) + CELL(0.918 ns) = 7.858 ns; Loc. = LC_X10_Y7_N6; Fanout = 1; REG Node = 'pspdata\[6\]~reg0'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.801 ns" { pspclk~reg0 pspdata[6]~reg0 } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 290 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.95 % ) " "Info: Total cell delay = 3.375 ns ( 42.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.483 ns ( 57.05 % ) " "Info: Total interconnect delay = 4.483 ns ( 57.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.858 ns" { clk pspclk~reg0 pspdata[6]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.858 ns" { clk clk~combout pspclk~reg0 pspdata[6]~reg0 } { 0.000ns 0.000ns 1.600ns 2.883ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 188 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 188; CLK Node = 'clk'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns RamC0\[6\] 2 REG LC_X10_Y7_N5 1 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X10_Y7_N5; Fanout = 1; REG Node = 'RamC0\[6\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk RamC0[6] } "NODE_NAME" } } { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 95 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamC0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamC0[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.858 ns" { clk pspclk~reg0 pspdata[6]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.858 ns" { clk clk~combout pspclk~reg0 pspdata[6]~reg0 } { 0.000ns 0.000ns 1.600ns 2.883ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamC0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamC0[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 95 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "PSP.v" "" { Text "D:/MYPSP测试程序/MYPSP/PSP.v" 290 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.858 ns" { clk pspclk~reg0 pspdata[6]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.858 ns" { clk clk~combout pspclk~reg0 pspdata[6]~reg0 } { 0.000ns 0.000ns 1.600ns 2.883ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamC0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamC0[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { RamC0[6] Selector41~13 pspdata[6]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.491 ns" { RamC0[6] Selector41~13 pspdata[6]~reg0 } { 0.000ns 0.000ns 0.305ns } { 0.000ns 0.595ns 0.591ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.858 ns" { clk pspclk~reg0 pspdata[6]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.858 ns" { clk clk~combout pspclk~reg0 pspdata[6]~reg0 } { 0.000ns 0.000ns 1.600ns 2.883ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk RamC0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout RamC0[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "clk 81 " "Warning: Can't achieve minimum setup and hold requirement clk along 81 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -