psp.tan.rpt

psp屏显示驱动程序cpld veriloghdl

Classic Timing Analyzer report for PSP
Sat Dec 01 21:14:06 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'WR'
  7. Clock Hold: 'clk'
  8. Clock Hold: 'WR'
  9. tsu
 10. tco
 11. th
 12. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                ;
+------------------------------+-----------+----------------------------------+----------------------------------+-------------+------------------+------------+----------+--------------+
; Type                         ; Slack     ; Required Time                    ; Actual Time                      ; From        ; To               ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+----------------------------------+-------------+------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A       ; None                             ; 4.542 ns                         ; RamData[12] ; RamB0[12]        ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A       ; None                             ; 20.637 ns                        ; LED~reg0    ; LED              ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A       ; None                             ; 2.049 ns                         ; wrdata[15]  ; WADDER[15]       ; --         ; WR       ; 0            ;
; Clock Setup: 'clk'           ; -4.219 ns ; 54.00 MHz ( period = 18.518 ns ) ; 37.10 MHz ( period = 26.956 ns ) ; addstart    ; RADDER[8]        ; clk        ; clk      ; 18           ;
; Clock Setup: 'WR'            ; 4.426 ns  ; 54.00 MHz ( period = 18.518 ns ) ; 70.96 MHz ( period = 14.092 ns ) ; WADDER[5]   ; wridata[9]       ; WR         ; WR       ; 0            ;
; Clock Hold: 'clk'            ; -2.556 ns ; 54.00 MHz ( period = 18.518 ns ) ; N/A                              ; RamB0[2]    ; pspdata[18]~reg0 ; clk        ; clk      ; 84           ;
; Clock Hold: 'WR'             ; 3.408 ns  ; 54.00 MHz ( period = 18.518 ns ) ; N/A                              ; WADDER[17]  ; WADDER[9]        ; WR         ; WR       ; 0            ;
; Total number of failed paths ;           ;                                  ;                                  ;             ;                  ;            ;          ; 102          ;
+------------------------------+-----------+----------------------------------+----------------------------------+-------------+------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM570T144C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;