psp.fit.rpt

psp屏显示驱动程序cpld veriloghdl

Fitter report for PSP
Sat Dec 01 21:13:18 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. Bidir Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Control Signals
 15. Global & Other Fast Signals
 16. Non-Global High Fan-Out Signals
 17. Interconnect Usage Summary
 18. LAB Logic Elements
 19. LAB-wide Signals
 20. LAB Signals Sourced
 21. LAB Signals Sourced Out
 22. LAB Distinct Inputs
 23. Fitter Device Options
 24. Advanced Data - General
 25. Advanced Data - Placement Preparation
 26. Advanced Data - Placement
 27. Advanced Data - Routing
 28. Fitter Messages
 29. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Sat Dec 01 21:13:18 2007    ;
; Quartus II Version    ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name         ; PSP                                      ;
; Top-level Entity Name ; PSP                                      ;
; Family                ; MAX II                                   ;
; Device                ; EPM570T144C5                             ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 386 / 570 ( 68 % )                       ;
; Total pins            ; 88 / 116 ( 76 % )                        ;
; Total virtual pins    ; 0                                        ;
; UFM blocks            ; 0 / 1 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EPM570T144C5                   ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;