f2407sci.c

TMS320F2407 filter 滤波程序

/************************************************************************/
/* Testprogram for serial communication SCI 							*/
/* running on TMS320LF2407 EVM 										 	*/
/* external clock is 14.7456 MHz, PLL * 2 , CPU-Clock then 29.49 MHz	*/
/************************************************************************/  
/************************************************************************/                                                                  
/* SCI-communication RS232 from EVA-board to PC- COM2				 	*/
/* Sending a String "2407 UART is fine !" to Windows-95 Hyperterminal	*/
/* 9600 Baud , 8bit, no parity , 1 Stopbit , no protocol				*/
/* Timer GPT2 starts transmission every 2.0 second						*/ 
/* program-name :  F2407SCI.c	/ project : lab7.mak					*/
/* date : 07/17/2001   (c) [e-mail]					*/											
/************************************************************************/

#include "regs2407.h"

/*************     SETUP for the MCRA - Register   **************/ 
#define MCRA15			0	/* 0 : IOPB7	1 : TCLKIN			*/
#define MCRA14			0	/* 0 : IOPB6	1 : TDIR			*/
#define MCRA13			0	/* 0 : IOPB5	1 : T2PWM			*/
#define MCRA12			0	/* 0 : IOPB4	1 : T1PWM			*/
#define MCRA11			0	/* 0 : IOPB3	1 : PWM6			*/
#define MCRA10			0	/* 0 : IOPB2	1 : PWM5			*/
#define MCRA9			0	/* 0 : IOPB1	1 : PWM4			*/
#define MCRA8			0   /* 0 : IOPB0	1 : PWM3			*/
#define MCRA7			0	/* 0 : IOPA7	1 : PWM2			*/
#define MCRA6			0	/* 0 : IOPA6	1 :	PWM1			*/
#define MCRA5			0	/* 0 : IOPA5	1 : CAP3			*/
#define MCRA4			0	/* 0 : IOPA4	1 :	CAP2/QEP2		*/
#define MCRA3			0	/* 0 : IOPA3	1 : CAP1/QEP1		*/
#define MCRA2			0	/* 0 : IOPA2	1 :	XINT1			*/
#define MCRA1			1	/* 0 : IOPA1	1 :	SCIRXD			*/
#define MCRA0			1	/* 0 : IOPA0	1 : SCITXD			*/
/****************************************************************/
/*************     SETUP for the MCRB - Register   **************/
#define MCRB9			0	/* 0 : IOPD1	1 : XINT2/EXTSOC	*/
#define MCRB8			1	/* 0 : CKLKOUT  1 : IOPD0			*/
#define MCRB7			0	/* 0 : IOPC7	1 : CANRX			*/
#define MCRB6			0	/* 0 : IOPC6	1 : CANTX			*/
#define MCRB5			0 	/* 0 : IOPC5	1 : SPISTE			*/
#define MCRB4			0	/* 0 : IOPC4	1 : SPICLK			*/
#define MCRB3			0	/* 0 : IOPC3	1 : SPISOMI			*/
#define MCRB2			0	/* 0 : IOPC2	1 : SPISIMO			*/
#define MCRB1			1	/* 0 : BIO		1 : IOPC1			*/
#define MCRB0			1	/* 0 : XF		1 : IOPC0			*/
/****************************************************************/
/*************     SETUP for the MCRC - Register   **************/ 
#define MCRC13			0	/* 0 : IOPF5	1 : TCLKIN2			*/
#define MCRC12			0	/* 0 : IOPF4	1 : TDIR2			*/
#define MCRC11			0	/* 0 : IOPF3	1 : T4PWM/T4CMP		*/
#define MCRC10			0	/* 0 : IOPF2	1 : T3PWM/T3CMP		*/
#define MCRC9			0	/* 0 : IOPF1	1 : CAP6			*/
#define MCRC8			0   /* 0 : IOPF0	1 : CAP5/QEP3		*/
#define MCRC7			0	/* 0 : IOPE7	1 : CAP4/QEP2		*/
#define MCRC6			0	/* 0 : IOPE6	1 :	PWM12			*/
#define MCRC5			0	/* 0 : IOPE5	1 : PWM11			*/
#define MCRC4			0	/* 0 : IOPE4	1 :	PWM10			*/
#define MCRC3			0	/* 0 : IOPE3	1 : PWM9			*/
#define MCRC2			0	/* 0 : IOPE2	1 :	PWM8			*/
#define MCRC1			0	/* 0 : IOPE1	1 :	PWM7			*/
#define MCRC0			0	/* 0 : IOPE0	1 : CLKOUT			*/
/****************************************************************/ 
/*************     SETUP for the WDCR - Register   **************/
#define WDDIS			1	/* 0 : Watchdog enabled 1: disabled */
#define WDCHK2			1	/* 0 : System reset   1: Normal OP	*/
#define WDCHK1			0	/* 0 : Normal Oper.	  1: sys reset	*/
#define WDCHK0			1	/* 0 : System reset   1: Normal OP	*/
#define WDSP			7	/* Watchdog prescaler 7 : div 64	*/
/****************************************************************/
/*************     SETUP for the SCSR1 - Register  **************/
#define CLKSRC			0	/* 0 : intern(30MHz)				*/
#define LPM				0	/* 0 : Low power mode 0 if idle		*/
#define CLK_PS			1	/* 001 : PLL multiply by 2			*/
#define ADC_CLKEN		0	/* 0 : No ADC-service in this test	*/
#define SCI_CLKEN		1   /* 1 : Use SCI-service in this test */
#define SPI_CLKEN		0	/* 0 : No SPI-servide in this test	*/
#define CAN_CLKEN		0	/* 0 : No CAN-service in this test	*/
#define EVB_CLKEN		0	/* 0 : No EVB-Service in this test	*/
#define EVA_CLKEN		1	/* 1 : Use EVA-Service in this test	*/
#define ILLADR			1	/* 1 : Clear ILLADR during startup	*/
/****************************************************************/ 
/*************     SETUP for the WSGR - Register   **************/
#define BVIS			0	/* 10-9 : 00 Bus visibility OFF		*/
#define ISWS			0	/* 8 -6 : 000 0 Waitstates for IO	*/
#define DSWS			0	/* 5 -3 : 000 0 Waitstates  data	*/
#define PSWS			0	/* 2 -0 : 000 0 Waitstaes code		*/
/****************************************************************/        
/*************     SETUP for the EVAIMRA - Register  ************/
#define T1OFINT			0  /* 10 : Timer 1 overflow interrupt	*/
#define T1UFINT			0  /*  9 : Timer 1 underflow interrupt 	*/ 
#define T1CINT			0  /*  8 : Timer 1 compare interrupt 	*/
#define T1PINT			0  /*  7 : Timer 1 period interrupt 	*/
#define	CMP3INT			0  /*  3 : Compare 3 interrupt			*/
#define CMP2INT			0  /*  2 : Compare 2 interrupt			*/
#define CMP1INT			0  /*  1 : Compare 1 interrupt			*/
#define PDPINT			0  /*  0 : Power Drive Protect Interrupt*/
/****************************************************************/
/*************     SETUP for the EVAIMRB - Register  ************/            
#define T2OFINT			0  /*  3 : Timer 2 overflow interrupt	*/
#define T2UFINT			0  /*  2 : Timer 2 underflow interrupt  */
#define T2CINT			0  /*  1 : Timer 2 compare interrupt	*/
#define T2PINT			1  /*  0 : Timer 2 period interrupt     */
/****************************************************************/
/*************     SETUP for the EVAIMRC- Register  *************/
#define CAP3INT			0  /*  2 : Capture Unit 3 interrupt		*/
#define CAP2INT			0  /*  1 : Capture Unit 2 Interrupt  	*/
#define CAP1INT			0  /*  0 : Capture unit 1 interrupt	    */
/****************************************************************/
/*************     SETUP for the IMR - Register    **************/
#define INT6			0  /*  5 : Level INT6  is masked 		*/
#define INT5			0  /*  4 : Level INT5  is masked		*/
#define INT4			0  /*  3 : Level INT4  is masked		*/
#define INT3			1  /*  2 : Level INT3  is unmasked 		*/
#define INT2			0  /*  1 : Level INT2  is masked		*/
#define INT1			1  /*  0 : Level INT1  is unmasked 	    */		
/*************     SETUP for the GPTCONA - Register  ********************/
#define GPTCONA_T2TOADC	0	/* 10-9 : 0 no ADC-Start by GPT2-Event		*/
#define GPTCONA_T1TOADC	0	/* 8-7  : 0 no ADC-Start by GPT1-Event		*/
#define GPTCONA_TCOMPOE 0	/* 6 : 0 disable all 2 GPT compare outputs 	*/
#define GPTCONA_T2PIN	0	/* 3-2 : 00 Pol. of GPT2 comp out=forced low*/
#define GPTCONA_T1PIN	0	/* 1-0 : 00 Pol. of GPT1 comp out=forced low*/
/************************************************************************/ 
/**************     SETUP for the T2CON - Register  *************/
#define T2CON_FREESOFT 	0  	/* 15-14 : 00 stop on JTAG suspend 	*/
#define T2CON_TMODE		2  	/* 12-11 : 10 Contiuous up counting	*/
#define T2CON_TPS		7   /* 10-8  :111 CPUCLK/128            */  
#define T2CON_TSWT1		0   /* 7	 :  0 use own TENABLE bit 	*/ 		  			 
#define T2CON_TENABLE	1   /* 6     :  1 Timer 2 enable 		*/
#define T2CON_TCLKS		0   /* 5-4   : 00 Clock source internal */
#define T2CON_TCLD		1   /* 3-2   : 01 reload when 0 or T2PR	*/
#define T2CON_TECMPR	1   /* 1     :  1 enable timer compare 	*/  
#define T2CON_SELT1PR	0   /* 0	 :  0 use T2 period register*/				 
/****************************************************************/
/*************     SETUP for the SCICCR - Register **************/
#define STOPBITS		0  /*  0 :  one stop bit				*/
#define EVENODD			0  /*  0 :  odd parity					*/
#define PARITY			0  /*  0 :  no parity					*/
#define LOOPBACKENA		0  /*  0 :  Loop Back Test Mode disabled*/
#define ADDRIDLE		0  /*  0 :  IDLE-line mode for multipr.	*/
#define SCICHAR			7  /*  111 : 8-bit data transmission  	*/
/****************************************************************/	            
/*************     SETUP for the SCICTL1 - Register *************/							   	                                      
#define RXERRINT		0  /*  0 : disable Rx Error Interrupts	*/
#define SWRESET			0  /*  0 : apply reset state			*/
						   /*  1 : reenabling SCI, after config.*/
#define TXWAKE			0  /*  0 : no wakeupfunction now		*/
#define SLEEP			0  /*  0 : sleep mode disabled			*/
#define TXENA			1  /*  1 : Transmitter enabled			*/
#define RXENA			0  /*  1 : Receiver  disabled			*/  
/****************************************************************/	            
/*************     SETUP for the SCICTL2 - Register *************/	
#define RXBKINT			0	/* 0 : disable RX and Break inter.	*/
#define TXINT			1	/* 1 : enable TXRDY-interrupt		*/
/****************************************************************/	            
/*************     SETUP for the SCIPRI - Register **************/
#define TXPRIORITY		0	/* TXD-int on high Priority (INT1)	*/
#define RXPRIORITY		0	/* RXD-int on high Priority (INT1)	*/
#define SCISOFTFREE		2	/* on emulator suspend complete SCI	*/
/****************************************************************/
#define PERIOD 46080	/* T2PER = 33,9084ns * 128 * 31250 =0.2s*/
#define BRR	383			/* baudrate register constant		    */
						/* 383 = (29,4912e+6/(9600Baud *8)) -1	*/ 			

static char index=0;
const char message[25]="The 2407 UART is fine !\n\r";

void c_dummy1(void)
{
	while(1);		/*Dummy ISR used to trap spurious interrupts*/
}
                
interrupt 	void T2PER_ISR(void)
{
	static unsigned char i=0;
	if((PIVR-0x002B)==0)	/* Verify T2PINT ( 0x002B)		*/
    {
	i++;
	if(i>=10){
			 /* wait for 10 * 0.2 s before start new transmission */
			 i=0;
			 SCITXBUF=message[index++];
			 }
	EVAIFRB=T2PINT;
	}
}		
		

interrupt 	void SCI_ISR(void)
{
 if((PIVR-0x0007)==0) 	/*Verify type of interrupt ( 7 = TxD )	*/
	{
	if(index<=24) SCITXBUF=message[index++]; /*transmit 		*/
	else index=0; 	/* end of transmission				 		*/
	}
}   

void main(void)
{
 asm (" setc INTM");/*Disable all interrupts					*/
 asm (" clrc SXM");	/*Clear Sign Extension Mode bit				*/
 asm (" clrc OVM");	/*Reset Overflow Mode bit*/
 asm (" clrc CNF");	/*Configure block B0 to data mem.			*/

 WSGR=((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS); 
 		 			/* set the external waitstates	 WSGR	    */
					
 WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);		
 					/* Initialize Watchdog-timer				*/
 
 SCSR1= ((CLKSRC<<14)+(LPM<<12)+(CLK_PS<<9)+(ADC_CLKEN<<7)+
 		 (SCI_CLKEN<<6)+(SPI_CLKEN<<5)+(CAN_CLKEN<<4)+
 		 (EVB_CLKEN<<3)+(EVA_CLKEN<<2)+ILLADR); 
 		   			/* Initialize SCSR1			 	 			*/ 
 		   			
 MCRC = ((MCRC13<<13)+(MCRC12<<12)+(MCRC11<<11)+(MCRC10<<10)
 		 +(MCRC9<<9)+(MCRC8<<8)+(MCRC7<<7)+(MCRC6<<6)
 		 +(MCRC5<<5)+(MCRC4<<4)+(MCRC3<<3)+(MCRC2<<2)
 		 +(MCRC1<<1)+MCRC0);	
          			/* Initialize multiplex control register C	*/  
 
 MCRB = ((MCRB9<<9)+(MCRB8<<8)+
 		  (MCRB7<<7)+(MCRB6<<6)+(MCRB5<<5)+(MCRB4<<4)+
 		  (MCRB3<<3)+(MCRB2<<2)+(MCRB1<<1)+MCRB0);
 		  			/* Initialize multiplex control register B	*/
 		  
  
 MCRA = ((MCRA15<<15)+(MCRA14<<14)+(MCRA13<<13)+(MCRA12<<12)+
          (MCRA11<<11)+(MCRA10<<10)+(MCRA9<<9)+(MCRA8<<8)+
          (MCRA7<<7)+(MCRA6<<6)+(MCRA5<<5)+(MCRA4<<4)+
          (MCRA3<<3)+(MCRA2<<2)+(MCRA1<<1)+MCRA0);	
          			/* Initialize multiplex control register A	*/  

 GPTCONA=((GPTCONA_T2TOADC<<9)+(GPTCONA_T1TOADC<<7)+
          (GPTCONA_TCOMPOE<<6)+(GPTCONA_T2PIN<<2)+
          (GPTCONA_T1PIN)); 	/*	Initialize GP Timer Control	*/ 
          
 T2PR = PERIOD;		/* initialize T2-period						*/
 T2CNT= 0x0000;		/* start value for T2-counter				*/			

 T2CON=((T2CON_FREESOFT<<14)+(T2CON_TMODE<<11)+(T2CON_TPS<<8)+
 	       (T2CON_TSWT1<<7)+(T2CON_TCLKS<<4)+(T2CON_TCLD<<2)+
 	       (T2CON_TECMPR<<1)+T2CON_SELT1PR);     
 	      
 SCICCR=((STOPBITS<<7)+(EVENODD<<6)+(PARITY<<5)+
         (LOOPBACKENA<<4)+(ADDRIDLE<<3)+SCICHAR);
          			/* Initialize SCI Control Register			*/

 SCICTL1=((RXERRINT<<6)+(SWRESET<<5)+
 		  (TXWAKE<<3)+(SLEEP<<2)+(TXENA<<1)+RXENA);	 	
					/* initialize SCI Control Register 1		*/  

 SCICTL2=((RXBKINT<<1)+TXINT);
 					/* initialize SCI Control Register 2		*/
  	
 SCIHBAUD=BRR>>8;	/* load the Baud-Rate Register				*/
 SCILBAUD=BRR & 0x00FF;        
 
 SCIPRI= ((TXPRIORITY<<6)+(RXPRIORITY<<5)+(SCISOFTFREE<<3));
 					/* Initialize SCI Priority control register */
 						
 SCICTL1|=0x0020;	/* reenable SCI ,  SWRESET=1				*/ 
 
 EVAIFRA=0xFFFF;   	/* clear EVA Interrupt Flags Group A		*/
		     		 
 EVAIFRB=0xFFFF;    /* clear EVA Interrupt Flags Group B 		*/
		     		 
 EVAIFRC=0xFFFF;    /* clear EVA Interrupt Flags Group C 		*/
 
 EVAIMRA=((T1OFINT<<10)+(T1UFINT<<9)+(T1CINT<<8)+
 	      (T1PINT<<7)+(CMP3INT<<3)+(CMP2INT<<2)+
 	      (CMP1INT<<1)+PDPINT);
 	         		/* enable specific EVA Interrupts Group A  	*/
		    
 EVAIMRB=((T2OFINT<<3)+(T2UFINT<<2)+(T2CINT<<1)+T2PINT);  
 					/* enable specific EVA Interrupts Group B 	*/
		    
 EVAIMRC=((CAP3INT<<2)+(CAP2INT<<1)+CAP1INT); 
  					/* enable specific EVA Interrupts Group C 	*/

 IFR=0xFFFF; 		/* Reset  all core interrupts			 	*/
 	
 IMR=((INT6<<5)+(INT5<<4)+(INT4<<3)+(INT3<<2)+(INT2<<1)+INT1);     
 					/* enable specific core Interrupts 			*/
		     
 asm (" clrc INTM");  /* Enable all unmasked interrupts		*/      
 
 T2CON=T2CON+(T2CON_TENABLE<<6); /* enable GPT2 now		*/  	  
 
 while(1);			/* endless loop ; action done by ISR	*/	                                                  
 
}