can_tra.c

TMS320F2407 filter 滤波程序

/************************************************************************/
/* Testprogram for CAN-transmission			 							*/
/* running on TMS320LF207 EVM											*/
/* external clock is 14.7456 MHz, PLL * 2 , CPU-Clock then 29.49 MHz	*/
/* date :  18/07/2001 ,  (C) [e-mail]				*/
/************************************************************************/                                                                  
/* CAN-Transmission 100 kBaud to CAN-Labnet	at FH Zwickau			 	*/
/* Standard - Frame : Identifier 0x0160									*/
/* transmit the  value of the DIP-switches(PEDATDIR) as 1 byte frame	*/
/* next transmission when the DIP-switch status has changed				*/
/* program-name :  can_tra.c	/ project : can_tra						*/											
/************************************************************************/

#include "regs2407.h"

/*************     SETUP for the MCRA - Register   **************/ 
#define MCRA15			0	/* 0 : IOPB7	1 : TCLKIN			*/
#define MCRA14			0	/* 0 : IOPB6	1 : TDIR			*/
#define MCRA13			0	/* 0 : IOPB5	1 : T2PWM			*/
#define MCRA12			0	/* 0 : IOPB4	1 : T1PWM			*/
#define MCRA11			0	/* 0 : IOPB3	1 : PWM6			*/
#define MCRA10			0	/* 0 : IOPB2	1 : PWM5			*/
#define MCRA9			0	/* 0 : IOPB1	1 : PWM4			*/
#define MCRA8			0   /* 0 : IOPB0	1 : PWM3			*/
#define MCRA7			0	/* 0 : IOPA7	1 : PWM2			*/
#define MCRA6			0	/* 0 : IOPA6	1 :	PWM1			*/
#define MCRA5			0	/* 0 : IOPA5	1 : CAP3			*/
#define MCRA4			0	/* 0 : IOPA4	1 :	CAP2/QEP2		*/
#define MCRA3			0	/* 0 : IOPA3	1 : CAP1/QEP1		*/
#define MCRA2			0	/* 0 : IOPA2	1 :	XINT1			*/
#define MCRA1			1	/* 0 : IOPA1	1 :	SCIRXD			*/
#define MCRA0			1	/* 0 : IOPA0	1 : SCITXD			*/
/****************************************************************/
/*************     SETUP for the MCRB - Register   **************/
#define MCRB9			0	/* 0 : IOPD1	1 : XINT2/EXTSOC	*/
#define MCRB8			1	/* 0 : CKLKOUT  1 : IOPD0			*/
#define MCRB7			1	/* 0 : IOPC7	1 : CANRX			*/
#define MCRB6			1	/* 0 : IOPC6	1 : CANTX			*/
#define MCRB5			0 	/* 0 : IOPC5	1 : SPISTE			*/
#define MCRB4			0	/* 0 : IOPC4	1 : SPICLK			*/
#define MCRB3			0	/* 0 : IOPC3	1 : SPISOMI			*/
#define MCRB2			0	/* 0 : IOPC2	1 : SPISIMO			*/
#define MCRB1			1	/* 0 : BIO		1 : IOPC1			*/
#define MCRB0			1	/* 0 : XF		1 : IOPC0			*/
/****************************************************************/ 
/*************     SETUP for the MCRC - Register   **************/ 
#define MCRC13			0	/* 0 : IOPF5	1 : TCLKIN2			*/
#define MCRC12			0	/* 0 : IOPF4	1 : TDIR2			*/
#define MCRC11			0	/* 0 : IOPF3	1 : T4PWM/T4CMP		*/
#define MCRC10			0	/* 0 : IOPF2	1 : T3PWM/T3CMP		*/
#define MCRC9			0	/* 0 : IOPF1	1 : CAP6			*/
#define MCRC8			0   /* 0 : IOPF0	1 : CAP5/QEP3		*/
#define MCRC7			0	/* 0 : IOPE7	1 : CAP4/QEP2		*/
#define MCRC6			0	/* 0 : IOPE6	1 :	PWM12			*/
#define MCRC5			0	/* 0 : IOPE5	1 : PWM11			*/
#define MCRC4			0	/* 0 : IOPE4	1 :	PWM10			*/
#define MCRC3			0	/* 0 : IOPE3	1 : PWM9			*/
#define MCRC2			0	/* 0 : IOPE2	1 :	PWM8			*/
#define MCRC1			0	/* 0 : IOPE1	1 :	PWM7			*/
#define MCRC0			0	/* 0 : IOPE0	1 : CLKOUT			*/
/****************************************************************/ 
/*************     SETUP for the WDCR - Register   **************/
#define WDDIS			1	/* 0 : Watchdog enabled 1: disabled */
#define WDCHK2			1	/* 0 : System reset   1: Normal OP	*/
#define WDCHK1			0	/* 0 : Normal Oper.	  1: sys reset	*/
#define WDCHK0			1	/* 0 : System reset   1: Normal OP	*/
#define WDSP			7	/* Watchdog prescaler 7 : div 64	*/
/****************************************************************/
/*************     SETUP for the SCSR1 - Register  **************/
#define CLKSRC			0	/* 0 : intern(30MHz)				*/
#define LPM				0	/* 0 : Low power mode 0 if idle		*/
#define CLK_PS			1	/* 001 : PLL multiply by 2			*/
#define ADC_CLKEN		0	/* 0 : No ADC-service in this test	*/
#define SCI_CLKEN		0   /* 0 : No SCI-service in this test  */
#define SPI_CLKEN		0	/* 0 : No SPI-servide in this test	*/
#define CAN_CLKEN		1	/* 1 : CAN-service in this test		*/
#define EVB_CLKEN		0	/* 0 : No EVB-Service in this test	*/
#define EVA_CLKEN		0	/* 0 : No EVA-Service in this test	*/
#define ILLADR			1	/* 1 : Clear ILLADR during startup	*/
/****************************************************************/ 
/*************     SETUP for the WSGR - Register   **************/
#define BVIS			0	/* 10-9 : 00 Bus visibility OFF		*/
#define ISWS			0	/* 8 -6 : 000 0 Waitstates for IO	*/
#define DSWS			0	/* 5 -3 : 000 0 Waitstates  data	*/
#define PSWS			0	/* 2 -0 : 000 0 Waitstaes code		*/
/****************************************************************/        
/*************     SETUP for the IMR - Register    **************/
#define INT6			0  /*  5 : Level INT6  is masked 		*/
#define INT5			0  /*  4 : Level INT5  is masked		*/
#define INT4			0  /*  3 : Level INT4  is masked		*/
#define INT3			0  /*  2 : Level INT3  is masked 		*/
#define INT2			0  /*  1 : Level INT2  is masked		*/
#define INT1			0  /*  0 : Level INT1  is masked 	    */		
/********************************************************************************/
/****** SETUP for the CAN Master Control  - Register ( CAN_MCR) 				*/
#define CAN_SUSP	0	/* 13 : Soft Mode : Stop CAN when Transmission complete */
#define CAN_CCR		1	/* 12 : write access to CAN-Configuration registers		*/
#define CAN_PDR		0	/* 11 :	no power down mode requested					*/ 
#define CAN_DBO		1	/* 10 : Data-Byte-Order : 0,1,2,3,4,5,6,7				*/
#define CAN_WUBA	0	/* 9  : Wake from power down only after write 0 to PDR 	*/
#define CAN_CDR		0	/* 8  : no "change data field request to any mailbox	*/
#define CAN_ABO		0	/* 7  : after "bus off" only wit reset return to CAN	*/
#define CAN_STM		0	/* 6  : no self test mode								*/ 
#define CAN_MBNR	0	/* 1-0: Mailbox Nr										*/
/********************************************************************************/
/******* SETUP for the Bit Configuration Register (CAN_BCR2 + CAN_BCR1)	*****/
/*			Setup for CAN with 100kHz because we have SLIO's in our net		*/
/*		100Khz : 1 bit time = 10祍 											*/
/*		  10祍 = (TSEG1 +TSEG2+1) *tquantum     							*/
/*			   = (  11   +  8  +1)*tquantum									*/
/*	  tquantum =  0,5 祍													*/
/*	  tquantum = (BRP +1 ) / Iclk 			( Iclk = 29.5MHz )				*/
/*		BRP	   =  (0,5e-6s * 29.5e+6/s) -1 = 13,75							*/
#define CAN_BRP		14	/* Baud rate prescaler								*/
#define CAN_SBG		1	/* synchronise CAN with both edges 					*/
#define CAN_SJW		2	/* Syncronisation jump width						*/
#define CAN_SAM		0	/* take only one sample per bit						*/
#define CAN_TSEG1	11-1/* Time Segment 1									*/
#define CAN_TSEG2	8-1	/* Time Segment 2									*/	
/****************************************************************************/
/****** SETUP for the CAN Mailbox Direction/Enable - Register ( CAN_MDER)	*/
#define CAN_MD		0	/* 7-6 : 00 both mailbox 2 and 3 are transmitters	*/
#define CAN_ME		0	/* 5-0 : mailbox 0 to 5 disabled					*/	 	
/****** SETUP for the CAN MAILBOX # 5  ( transmit)							*/	
#define MB5_IDE		0	/* 11-bit identifier only							*/
#define MB5_AME		0	/* the local acceptance mask is enabled				*/
#define MB5_AAM		0	/* no reply to a remote request						*/
#define MB5_ID_STD	0x0160 /* Standard-Identifier bit11-0 to be transmitted	*/
#define MB5_ID_EXTL 0x0000 /* extended identifier bits 15-0					*/ 	


/****************************************************************/
/*			Function deklarations								*/
/****************************************************************/
void can_transmit5(void);
void can_mailbox5(unsigned char mess);
void can_init(void);
void c_dummy1(void);
/****************************************************************/
/*			Global Variable Definition							*/
/****************************************************************/
                                /* pointer to 6 CAN -mailboxes	*/
unsigned int *CANMSGIDL[6];		/* Message -identifier	low word*/
unsigned int *CANMSGIDH[6];		/* MEssage -identifier high word*/ 	
unsigned int *CANMSGCTRL[6];	/* Message control				*/
unsigned int *CANDATA0[6];		/* Data Byte 0 of the messages	*/
unsigned char DIP_SWITCH=0xFF;
 

void can_init(void)
{
	unsigned int i;
	for (i=0;i<6;i++){
						/* setup the pointer arrays to mailboxes	*/
		CANMSGIDL[i]  = (unsigned int *)(0x7200 +i*8);     
		CANMSGIDH[i]  = (unsigned int *)(0x7201 +i*8);
        CANMSGCTRL[i]= (unsigned int *)(0x7202 +i*8);  
		CANDATA0[i]	 = (unsigned int *)(0x7204 +i*8); 
        }
			/* Initialize the Master Control Registers				*/
		CAN_MCR |= ((CAN_SUSP<<13)+(CAN_CCR<<12)+(CAN_PDR<<11)+
					 (CAN_DBO<<10)+(CAN_WUBA<<9)+(CAN_CDR<<8)+
					 (CAN_ABO<<7)+(CAN_STM<<6)+	CAN_MBNR );
			/* Wait for Change configuration enable CCR				*/
		while((CAN_GSR & 0x0010) == 0 );/* DANGER for endless lock!!*/
			/* Initialize CAN-Baudrate	CAN_BCR2 and CAN_BCR1		*/
		CAN_BCR2 = CAN_BRP;
		CAN_BCR1 = ((CAN_SBG<<10)+(CAN_SJW<<8)+(CAN_SAM<<7)+       
					 (CAN_TSEG1<<3)+(CAN_TSEG2));    
		CAN_MCR &= 0xEFFF;	/* clear CAN_CCR -bit (bit 12)			*/     
        	/* Wait until the CCE-Bit in CAN_GSR is set				*/
        while((CAN_GSR & 0x0010) != 0 );/* DANGER for endless lock	*/
			/* disable first all 6 mailboxes						*/
		CAN_MDER = ((CAN_MD<<6)+CAN_ME);
}


void can_transmit5(void)
{
 	CAN_TCR = 0x0080;		/* transmit request set (TRS)mailbox#5	*/
 	while((CAN_TCR & 0x8000) ==0); /* wait for transmit ACK    		*/          
 								/* mailbox #5 : Bit 15 = 1			*/
 								/* DANGER endless lock				*/
	
 	while((CAN_IFR &= 0x2000)==0); 		/* wait for MIF5= 1			*/	
	
	 	
	CAN_TCR |= 0x8000;				/* Reset TA and interrupt flag	*/
}
    
void can_mailbox5(unsigned char mess)
{
		/*  now enable access to data fields (CAN_MCR-bit 8 = 1)	*/
		CAN_MCR |= 0x0100;	
		/* prepare mailbox #5 for transmission						*/
		*CANMSGIDH[5]=((MB5_IDE<<15)+(MB5_AME<<14)+(MB5_AAM)+
					   (MB5_ID_STD<<2));
		*CANMSGIDL[5]= MB5_ID_EXTL; 	  
		*CANMSGCTRL[5]=0x0001;
			/* Bit 4 : RTR = 0 : data frame							
			       3-0 DLC = 0001 = 1 Byte							*/
		*CANDATA0[5] = mess;	/* data to be transmitted			*/		
		/* now disable access to data fields (CAN_MCR bit 8 = 0)	*/
		CAN_MCR &= 0xFEFF ;
		/* now enable mailbox #5 as transmitter						*/
		CAN_MDER = 0x0020;		/* enable mailbox#5					*/ 
		CAN_IMR =  0x2000;		/* enable mailbox#5 interrupt		*/
}
    
void c_dummy1(void)
{
	while(1);		/*Dummy ISR used to trap spurious interrupts*/
}
                

void main(void)
{
 asm (" setc INTM");/*Disable all interrupts					*/
 asm (" clrc SXM");	/*Clear Sign Extension Mode bit				*/
 asm (" clrc OVM");	/*Reset Overflow Mode bit*/
 asm (" clrc CNF");	/*Configure block B0 to data mem.			*/

 WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);		
 					/* Initialize Watchdog-timer				*/
 
 SCSR1= ((CLKSRC<<14)+(LPM<<12)+(CLK_PS<<9)+(ADC_CLKEN<<7)+
 		   (SCI_CLKEN<<6)+(SPI_CLKEN<<5)+(CAN_CLKEN<<4)+
 		   (EVB_CLKEN<<3)+(EVA_CLKEN<<2)+ILLADR); 
 		   
 WSGR = ((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS); /* set waitstates */
					
 MCRB = ((MCRB9<<9)+(MCRB8<<8)+
 		  	(MCRB7<<7)+(MCRB6<<6)+(MCRB5<<5)+(MCRB4<<4)+
 		  	(MCRB3<<3)+(MCRB2<<2)+(MCRB1<<1)+MCRB0);
 	  				/* Initialize master control register B		*/
 		  
 MCRA = ((MCRA15<<15)+(MCRA14<<14)+(MCRA13<<13)+(MCRA12<<12)+
          	(MCRA11<<11)+(MCRA10<<10)+(MCRA9<<9)+(MCRA8<<8)+
          	(MCRA7<<7)+(MCRA6<<6)+(MCRA5<<5)+(MCRA4<<4)+
          	(MCRA3<<3)+(MCRA2<<2)+(MCRA1<<1)+MCRA0);	
      				/* Initialize master control register A		*/      
 
 MCRC = ((MCRC13<<13)+(MCRC12<<12)+(MCRC11<<11)+(MCRC10<<10)
 		 	+(MCRC9<<9)+(MCRC8<<8)+(MCRC7<<7)+(MCRC6<<6)
 		 	+(MCRC5<<5)+(MCRC4<<4)+(MCRC3<<3)+(MCRC2<<2)
 		 	+(MCRC1<<1)+MCRC0);	
       				/* Initialize master control register C		*/ 
  
 IFR=0xFFFF;       		/* Reset  all core interrupts			*/
		      
 IMR=((INT6<<5)+(INT5<<4)+(INT4<<3)+(INT3<<2)+(INT2<<1)+
       (INT1));     	 /* Interrupt Mask Register				*/
		     
 can_init();                         

 asm (" clrc INTM");  	/* Enable all unmasked interrupts		*/      
 
 PEDATDIR=0xFF00;       /* switch-off LED's						*/
 
 while(1)			
    {
 	while( (PBDATDIR & 0x00FF) == DIP_SWITCH );  
 	DIP_SWITCH = (PBDATDIR & 0x00FF);
 	can_mailbox5(DIP_SWITCH);
 	can_transmit5(); 
    }                
 }