light.syr

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

#      20-bit adder                : 2
#      28-bit adder                : 3
# Comparators                      : 12
#      20-bit comparator greatequal: 2
#      20-bit comparator less      : 2
#      28-bit comparator greatequal: 1
#      32-bit comparator less      : 2
#      4-bit comparator greater    : 2
#      4-bit comparator lessequal  : 2
#      5-bit comparator greatequal : 1

Cell Usage :
# BELS                             : 855
#      GND                         : 1
#      LUT1                        : 129
#      LUT1_L                      : 20
#      LUT2                        : 39
#      LUT2_D                      : 2
#      LUT2_L                      : 10
#      LUT3                        : 88
#      LUT3_L                      : 62
#      LUT4                        : 86
#      LUT4_D                      : 6
#      LUT4_L                      : 6
#      MUXCY                       : 257
#      MUXF5                       : 11
#      VCC                         : 1
#      XORCY                       : 137
# FlipFlops/Latches                : 189
#      FD                          : 9
#      FDE                         : 139
#      FDR                         : 28
#      FDRE                        : 5
#      FDS                         : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 14
#      IBUF                        : 2
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     239  out of   3584     6%  
 Number of Slice Flip Flops:           189  out of   7168     2%  
 Number of 4 input LUTs:               448  out of   7168     6%  
 Number of bonded IOBs:                 14  out of    141     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
GCLK                               | BUFGP                  | 144   |
divclk:Q                           | NONE                   | 45    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 11.162ns (Maximum Frequency: 89.589MHz)
   Minimum input arrival time before clock: 6.008ns
   Maximum output required time after clock: 9.363ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'GCLK'
Delay:               11.162ns (Levels of Logic = 51)
  Source:            divtenmsb_7 (FF)
  Destination:       delayb_31 (FF)
  Source Clock:      GCLK rising
  Destination Clock: GCLK rising

  Data Path: divtenmsb_7 to delayb_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              5   0.619   0.658  divtenmsb_7 (divtenmsb_7)
     LUT1_L:I0->LO         1   0.720   0.000  divtenmsb<7>_rt (divtenmsb<7>_rt)
     MUXCY:S->O            1   0.629   0.000  Mcompar__n0052_inst_cy_57 (Mcompar__n0052_inst_cy_57)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_58 (Mcompar__n0052_inst_cy_58)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_59 (Mcompar__n0052_inst_cy_59)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_60 (Mcompar__n0052_inst_cy_60)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_61 (Mcompar__n0052_inst_cy_61)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_62 (Mcompar__n0052_inst_cy_62)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_63 (Mcompar__n0052_inst_cy_63)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_64 (Mcompar__n0052_inst_cy_64)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_65 (Mcompar__n0052_inst_cy_65)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_66 (Mcompar__n0052_inst_cy_66)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_67 (Mcompar__n0052_inst_cy_67)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_68 (Mcompar__n0052_inst_cy_68)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_69 (Mcompar__n0052_inst_cy_69)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_70 (Mcompar__n0052_inst_cy_70)
     MUXCY:CI->O           1   0.090   0.000  Mcompar__n0052_inst_cy_71 (Mcompar__n0052_inst_cy_71)
     MUXCY:CI->O          54   0.331   1.343  Mcompar__n0052_inst_cy_72 (_n0052)
     LUT2_L:I0->LO         1   0.720   0.000  _n00421 (_n0042)
     MUXCY:S->O            1   0.629   0.000  delayb_inst_cy_0 (delayb_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_1 (delayb_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_2 (delayb_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_3 (delayb_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_4 (delayb_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_5 (delayb_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_6 (delayb_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_7 (delayb_inst_cy_7)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_8 (delayb_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_9 (delayb_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_10 (delayb_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_11 (delayb_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_12 (delayb_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_13 (delayb_inst_cy_13)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_14 (delayb_inst_cy_14)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_15 (delayb_inst_cy_15)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_16 (delayb_inst_cy_16)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_17 (delayb_inst_cy_17)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_18 (delayb_inst_cy_18)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_19 (delayb_inst_cy_19)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_20 (delayb_inst_cy_20)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_21 (delayb_inst_cy_21)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_22 (delayb_inst_cy_22)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_23 (delayb_inst_cy_23)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_24 (delayb_inst_cy_24)
     MUXCY:CI->O           1   0.091   0.000  delayb_inst_cy_25 (delayb_inst_cy_25)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_26 (delayb_inst_cy_26)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_27 (delayb_inst_cy_27)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_28 (delayb_inst_cy_28)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_29 (delayb_inst_cy_29)
     MUXCY:CI->O           1   0.090   0.000  delayb_inst_cy_30 (delayb_inst_cy_30)
     MUXCY:CI->O           0   0.090   0.000  delayb_inst_cy_31 (delayb_inst_cy_31)
     XORCY:CI->O           1   0.939   0.000  delayb_inst_sum_31 (delayb_inst_sum_31)
     FDE:D                     0.502          delayb_31
    ----------------------------------------
    Total                     11.162ns (9.161ns logic, 2.001ns route)
                                       (82.1% logic, 17.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'divclk:Q'
Delay:               8.232ns (Levels of Logic = 5)
  Source:            stopcounterb_0 (FF)
  Destination:       sec_a_2 (FF)
  Source Clock:      divclk:Q rising
  Destination Clock: divclk:Q rising

  Data Path: stopcounterb_0 to sec_a_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              6   0.619   0.688  stopcounterb_0 (stopcounterb_0)
     LUT4_D:I1->O          5   0.720   0.658  Mcompar__n0066_Ker39981 (Mcompar__n0066_N4000)
     LUT2:I1->O           19   0.720   1.102  Ker108321 (N10834)
     LUT4:I3->O            1   0.720   0.000  Ker10975_F (N13962)
     MUXF5:I0->O           2   0.387   0.465  Ker10975 (N10977)
     LUT4:I0->O            1   0.720   0.240  _n0032<2>26 (CHOICE134)
     FDS:S                     1.193          sec_b_2
    ----------------------------------------
    Total                      8.232ns (5.079ns logic, 3.153ns route)
                                       (61.7% logic, 38.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'GCLK'
Offset:              6.008ns (Levels of Logic = 3)
  Source:            set1 (PAD)
  Destination:       delaya_29 (FF)
  Destination Clock: GCLK rising

  Data Path: set1 to delaya_29
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            22   1.492   1.207  set1_IBUF (set1_IBUF)
     LUT2_D:I1->O          1   0.720   0.240  _n0038_SW0 (N12603)
     LUT4:I3->O           16   0.720   0.995  _n0038_1 (_n0038_1)
     FDE:CE                    0.634          delaya_9
    ----------------------------------------
    Total                      6.008ns (3.566ns logic, 2.442ns route)
                                       (59.4% logic, 40.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'GCLK'
Offset:              8.550ns (Levels of Logic = 3)
  Source:            scan_7 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      GCLK rising

  Data Path: scan_7 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              21   0.619   1.172  scan_7 (scan_7)
     LUT3:I0->O            1   0.720   0.000  Mmux_N_inst_lut3_341 (Mmux_N__net4)
     MUXF5:I0->O           1   0.387   0.240  Mmux_N_inst_mux_f5_1 (N_1_OBUF)
     OBUF:I->O                 5.412          N_1_OBUF (N<1>)
    ----------------------------------------
    Total                      8.550ns (7.138ns logic, 1.412ns route)
                                       (83.5% logic, 16.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'divclk:Q'
Offset:              9.363ns (Levels of Logic = 4)
  Source:            state_a_2 (FF)
  Destination:       N<5> (PAD)
  Source Clock:      divclk:Q rising

  Data Path: state_a_2 to N<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              6   0.619   0.688  state_a_2 (state_a_2)
     LUT4:I0->O            3   0.720   0.577  StaSega<5>1 (StaSega<5>)
     LUT3:I1->O            1   0.720   0.000  Mmux_N_inst_lut3_361 (Mmux_N__net7)
     MUXF5:I0->O           1   0.387   0.240  Mmux_N_inst_mux_f5_2 (N_2_OBUF)
     OBUF:I->O                 5.412          N_2_OBUF (N<2>)
    ----------------------------------------
    Total                      9.363ns (7.858ns logic, 1.505ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================
CPU : 11.52 / 11.94 s | Elapsed : 11.00 / 12.00 s
 
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Total memory usage is 74400 kilobytes