light.syr

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: light.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : light.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : light
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : light
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : light.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/LIGHT is now defined in a different file: was F:/xilinxProject/lighttest/light.vhd, now is F:/xilinxProject/light/light.vhd
WARNING:HDLParsers:3215 - Unit work/LIGHT/BEHAVIORAL is now defined in a different file: was F:/xilinxProject/lighttest/light.vhd, now is F:/xilinxProject/light/light.vhd
Compiling vhdl file F:/xilinxProject/light/light.vhd in Library work.
Entity <light> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <light> (Architecture <behavioral>).
INFO:Xst:1561 - F:/xilinxProject/light/light.vhd line 74: Mux is complete : default of case is discarded
WARNING:Xst:819 - F:/xilinxProject/light/light.vhd line 60: The following signals are missing in the process sensitivity list:
   SecSega, StaSega, StaSegb, SecSegb.
Entity <light> analyzed. Unit <light> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <light>.
    Related source file is F:/xilinxProject/light/light.vhd.
    Using one-hot encoding for signal <state_a>.
    Using one-hot encoding for signal <state_b>.
    Found 16x8-bit ROM for signal <SecSega>.
    Found 16x8-bit ROM for signal <SecSegb>.
    Found 8-bit 4-to-1 multiplexer for signal <N>.
    Found 28-bit comparator greatequal for signal <$n0027> created at line 40.
    Found 4-bit subtractor for signal <$n0047>.
    Found 4-bit subtractor for signal <$n0048>.
    Found 20-bit comparator greatequal for signal <$n0050> created at line 279.
    Found 20-bit comparator greatequal for signal <$n0052> created at line 311.
    Found 4-bit comparator lessequal for signal <$n0063> created at line 189.
    Found 4-bit comparator greater for signal <$n0064> created at line 189.
    Found 4-bit comparator lessequal for signal <$n0065> created at line 194.
    Found 4-bit comparator greater for signal <$n0066> created at line 194.
    Found 4-bit adder for signal <$n0077> created at line 166.
    Found 4-bit adder for signal <$n0078> created at line 185.
    Found 5-bit comparator greatequal for signal <$n0079> created at line 203.
    Found 20-bit comparator less for signal <$n0080> created at line 279.
    Found 32-bit comparator less for signal <$n0081> created at line 269.
    Found 20-bit comparator less for signal <$n0082> created at line 311.
    Found 32-bit comparator less for signal <$n0083> created at line 301.
    Found 20-bit adder for signal <$n0084> created at line 276.
    Found 20-bit adder for signal <$n0085> created at line 308.
    Found 1-bit register for signal <blocka>.
    Found 1-bit register for signal <blockb>.
    Found 32-bit up counter for signal <delaya>.
    Found 32-bit up counter for signal <delayb>.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 20-bit register for signal <divtenmsa>.
    Found 20-bit register for signal <divtenmsb>.
    Found 4-bit register for signal <restore_seca>.
    Found 4-bit register for signal <restore_secb>.
    Found 4-bit register for signal <restore_statea>.
    Found 4-bit register for signal <restore_stateb>.
    Found 9-bit up counter for signal <scan>.
    Found 4-bit register for signal <sec_a>.
    Found 4-bit register for signal <sec_b>.
    Found 4-bit register for signal <state_a>.
    Found 4-bit register for signal <state_b>.
    Found 4-bit register for signal <stopcountera>.
    Found 4-bit register for signal <stopcounterb>.
    Found 5-bit up counter for signal <temp>.
    Summary:
	inferred   2 ROM(s).
	inferred   5 Counter(s).
	inferred  83 D-type flip-flop(s).
	inferred   6 Adder/Subtracter(s).
	inferred  12 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <light> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
  16x8-bit ROM                     : 2
# Registers                        : 15
  1-bit register                   : 3
  4-bit register                   : 10
  20-bit register                  : 2
# Counters                         : 5
  28-bit up counter                : 1
  9-bit up counter                 : 1
  5-bit up counter                 : 1
  32-bit up counter                : 2
# Multiplexers                     : 1
  8-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 6
  4-bit subtractor                 : 2
  4-bit adder                      : 2
  20-bit adder                     : 2
# Comparators                      : 12
  28-bit comparator greatequal     : 1
  20-bit comparator greatequal     : 2
  4-bit comparator lessequal       : 2
  4-bit comparator greater         : 2
  5-bit comparator greatequal      : 1
  20-bit comparator less           : 2
  32-bit comparator less           : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <light> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block light, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : light.ngr
Top Level Output File Name         : light
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Macro Statistics :
# ROMs                             : 2
#      16x8-bit ROM                : 2
# Registers                        : 18
#      1-bit register              : 3
#      20-bit register             : 2
#      28-bit register             : 3
#      4-bit register              : 10
# Counters                         : 2
#      32-bit up counter           : 2
# Multiplexers                     : 1
#      8-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 5