coregen.log

来自「A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.1i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\xilinxProject\light\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\xilinxProject\light
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=F:\xilinxProject\light
SETPROJECT .
Set current Project to F:\xilinxProject\light
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1499
XIPCPJSENDCORES spartan3