__projnav.log

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/xilinxProject/lighttest/light.vhd in Library work.
Entity <light> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <light> (Architecture <behavioral>).
INFO:Xst:1561 - F:/xilinxProject/lighttest/light.vhd line 76: Mux is complete : default of case is discarded
WARNING:Xst:819 - F:/xilinxProject/lighttest/light.vhd line 62: The following signals are missing in the process sensitivity list:
   SecSega, StaSega, StaSegb, SecSegb.
WARNING:Xst:819 - F:/xilinxProject/lighttest/light.vhd line 218: The following signals are missing in the process sensitivity list:
   divtenms.
INFO:Xst:1304 - Contents of register <blockab> in unit <light> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <blockab> in unit <light> never changes during circuit operation. The register is replaced by logic.
Entity <light> analyzed. Unit <light> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <light>.
    Related source file is F:/xilinxProject/lighttest/light.vhd.
WARNING:Xst:1780 - Signal <storetemp> is never used or assigned.
WARNING:Xst:1780 - Signal <stopcounter> is never used or assigned.
    Using one-hot encoding for signal <state_a>.
    Using one-hot encoding for signal <state_b>.
    Using one-hot encoding for signal <blockab>.
    Found 16x8-bit ROM for signal <SecSega>.
    Found 16x8-bit ROM for signal <SecSegb>.
    Found 8-bit 4-to-1 multiplexer for signal <N>.
    Found 28-bit comparator greatequal for signal <$n0007> created at line 42.
    Found 5-bit comparator greatequal for signal <$n0009> created at line 145.
    Found 4-bit subtractor for signal <$n0034> created at line 211.
    Found 4-bit subtractor for signal <$n0042> created at line 212.
    Found 20-bit comparator greatequal for signal <$n0043> created at line 228.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 20-bit up counter for signal <divtenms>.
    Found 9-bit up counter for signal <scan>.
    Found 4-bit register for signal <sec_a>.
    Found 4-bit register for signal <sec_b>.
    Found 4-bit register for signal <state_a>.
    Found 4-bit register for signal <state_b>.
    Found 5-bit up counter for signal <temp>.
    Summary:
	inferred   2 ROM(s).
	inferred   5 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <light> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
  16x8-bit ROM                     : 2
# Registers                        : 5
  4-bit register                   : 4
  1-bit register                   : 1
# Counters                         : 5
  28-bit up counter                : 1
  9-bit up counter                 : 1
  5-bit up counter                 : 1
  20-bit up counter                : 2
# Multiplexers                     : 1
  8-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 2
  4-bit subtractor                 : 2
# Comparators                      : 3
  28-bit comparator greatequal     : 1
  5-bit comparator greatequal      : 1
  20-bit comparator greatequal     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <light> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block light, actual ratio is 2.
FlipFlop temp_0 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      76  out of   3584     2%  
 Number of Slice Flip Flops:            60  out of   7168     0%  
 Number of 4 input LUTs:               144  out of   7168     2%  
 Number of bonded IOBs:                 12  out of    141     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
GCLK                               | BUFGP                  | 38    |
divclk:Q                           | NONE                   | 22    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.296ns (Maximum Frequency: 137.071MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.333ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\xilinxproject\lighttest/_ngo -uc
light.ucf -p xc3s400-pq208-4 light.ngc light.ngd 

Reading NGO file "F:/xilinxProject/lighttest/light.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "light.ucf" ...
ERROR:NgdBuild:755 - Line 14 in 'light.ucf': Could not find net(s) 'set1' in the
   design.  To suppress this error specify the correct net name or remove the
   constraint.  The 'Ignore I\O constraints on Invalid Object Names' property
   can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "light.ucf".

Writing NGDBUILD log file "light.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/xilinxProject/lighttest/light.vhd in Library work.
Entity <light> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <light> (Architecture <behavioral>).
INFO:Xst:1561 - F:/xilinxProject/lighttest/light.vhd line 76: Mux is complete : default of case is discarded
WARNING:Xst:819 - F:/xilinxProject/lighttest/light.vhd line 62: The following signals are missing in the process sensitivity list:
   SecSega, StaSega, StaSegb, SecSegb.
WARNING:Xst:819 - F:/xilinxProject/lighttest/light.vhd line 221: The following signals are missing in the process sensitivity list:
   divtenms.
INFO:Xst:1304 - Contents of register <blockab> in unit <light> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <blockab> in unit <light> never changes during circuit operation. The register is replaced by logic.
Entity <light> analyzed. Unit <light> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <light>.
    Related source file is F:/xilinxProject/lighttest/light.vhd.
WARNING:Xst:1780 - Signal <storetemp> is never used or assigned.
WARNING:Xst:1780 - Signal <stopcounter> is never used or assigned.
    Using one-hot encoding for signal <state_a>.
    Using one-hot encoding for signal <state_b>.
    Using one-hot encoding for signal <blockab>.
    Found 16x8-bit ROM for signal <SecSega>.
    Found 16x8-bit ROM for signal <SecSegb>.
    Found 8-bit 4-to-1 multiplexer for signal <N>.
    Found 28-bit comparator greatequal for signal <$n0007> created at line 42.
    Found 5-bit comparator greatequal for signal <$n0009> created at line 145.
    Found 4-bit subtractor for signal <$n0034> created at line 214.
    Found 4-bit subtractor for signal <$n0042> created at line 215.
    Found 20-bit comparator greatequal for signal <$n0043> created at line 231.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 20-bit up counter for signal <divtenms>.
    Found 9-bit up counter for signal <scan>.
    Found 4-bit register for signal <sec_a>.
    Found 4-bit register for signal <sec_b>.
    Found 4-bit register for signal <state_a>.
    Found 4-bit register for signal <state_b>.
    Found 5-bit up counter for signal <temp>.
    Summary:
	inferred   2 ROM(s).
	inferred   5 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <light> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
  16x8-bit ROM                     : 2
# Registers                        : 5
  4-bit register                   : 4
  1-bit register                   : 1
# Counters                         : 5
  28-bit up counter                : 1
  9-bit up counter                 : 1
  5-bit up counter                 : 1
  20-bit up counter                : 2
# Multiplexers                     : 1
  8-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 2
  4-bit subtractor                 : 2
# Comparators                      : 3
  28-bit comparator greatequal     : 1
  5-bit comparator greatequal      : 1
  20-bit comparator greatequal     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <light> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block light, actual ratio is 2.
FlipFlop temp_0 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      76  out of   3584     2%  
 Number of Slice Flip Flops:            60  out of   7168     0%  
 Number of 4 input LUTs:               144  out of   7168     2%  
 Number of bonded IOBs:                 12  out of    141     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
GCLK                               | BUFGP                  | 38    |
divclk:Q                           | NONE                   | 22    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.296ns (Maximum Frequency: 137.071MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.333ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".