__projnav.log

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

  2.481      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  65 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file light.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sun Jul 16 08:42:29 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module light . . .
PAR command line: par -w -intstyle ise -ol std -t 1 light_map.ncd light.ncd light.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
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Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\xilinxproject\lighttest/_ngo -uc
light.ucf -p xc3s400-pq208-4 light.ngc light.ngd 

Reading NGO file "F:/xilinxProject/lighttest/light.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "light.ucf" ...
ERROR:NgdBuild:755 - Line 15 in 'light.ucf': Could not find net(s) 'set2' in the
   design.  To suppress this error specify the correct net name or remove the
   constraint.  The 'Ignore I\O constraints on Invalid Object Names' property
   can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "light.ucf".

Writing NGDBUILD log file "light.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\xilinxproject\lighttest/_ngo -uc
light.ucf -p xc3s400-pq208-4 light.ngc light.ngd 

Reading NGO file "F:/xilinxProject/lighttest/light.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "light.ucf" ...
ERROR:NgdBuild:755 - Line 15 in 'light.ucf': Could not find net(s) 'set2' in the
   design.  To suppress this error specify the correct net name or remove the
   constraint.  The 'Ignore I\O constraints on Invalid Object Names' property
   can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "light.ucf".

Writing NGDBUILD log file "light.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\xilinxproject\lighttest/_ngo -uc
light.ucf -p xc3s400-pq208-4 light.ngc light.ngd 

Reading NGO file "F:/xilinxProject/lighttest/light.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "light.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40372 kilobytes

Writing NGD file "light.ngd" ...

Writing NGDBUILD log file "light.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s400pq208-4".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          60 out of   7,168    1%
  Number of 4 input LUTs:              99 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                           75 out of   3,584    2%
    Number of Slices containing only related logic:      75 out of      75  100%
    Number of Slices containing unrelated logic:          0 out of      75    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            142 out of   7,168    1%
  Number used as logic:                 99
  Number used as a route-thru:          43
  Number of bonded IOBs:               14 out of     141    9%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  1,386
Additional JTAG gate count for IOBs:  672
Peak Memory Usage:  73 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "light_map.mrp" for details.
Completed process "Map".

Mapping Module light . . .
MAP command line:
map -intstyle ise -p xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o light_map.ncd light.ngd light.pcf
Mapping Module light: DONE



Started process "Place & Route".





Constraints file: light.pcf

Loading device database for application Par from file "light_map.ncd".
   "light" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            14 out of 141     9%
      Number of LOCed External IOBs   14 out of 14    100%

   Number of SLICELs                  75 out of 3584    2%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897f3) REAL time: 0 secs 

Phase 3.8
.........
Phase 3.8 (Checksum:98f75a) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file light.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 488 unrouted;       REAL time: 0 secs 

Phase 2: 447 unrouted;       REAL time: 0 secs 

Phase 3: 159 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|        GCLK_BUFGP       |  BUFGMUX0| No   |   20 |  0.086     |  0.459      |
+-------------------------+----------+------+------+------------+-------------+
|            divclk       |   Local  |      |   18 |  0.015     |  2.481      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  65 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file light.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sun Jul 16 08:43:58 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module light . . .
PAR command line: par -w -intstyle ise -ol std -t 1 light_map.ncd light.ncd light.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
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Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/xilinxProject/lighttest/light.vhd in Library work.
Entity <light> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <light> (Architecture <behavioral>).
INFO:Xst:1561 - F:/xilinxProject/lighttest/light.vhd line 76: Mux is complete : default of case is discarded
WARNING:Xst:819 - F:/xilinxProject/lighttest/light.vhd line 62: The following signals are missing in the process sensitivity list:
   SecSega, StaSega, StaSegb, SecSegb.