light.mrp

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

Release 6.1i Map G.23
Xilinx Mapping Report File for Design 'light'

Design Information
------------------
Command Line   : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o light_map.ncd light.ngd light.pcf 
Target Device  : x3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.16 $
Mapped Date    : Sun Jul 16 15:25:24 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:         189 out of   7,168    2%
  Number of 4 input LUTs:             341 out of   7,168    4%
Logic Distribution:
  Number of occupied Slices:                          238 out of   3,584    6%
    Number of Slices containing only related logic:     238 out of     238  100%
    Number of Slices containing unrelated logic:          0 out of     238    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            448 out of   7,168    6%
  Number used as logic:                341
  Number used as a route-thru:         107
  Number of bonded IOBs:               15 out of     141   10%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  4,776
Additional JTAG gate count for IOBs:  720
Peak Memory Usage:  75 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Pack:266 - The function generator _n00731 failed to merge with F5
   multiplexer Ker10970.  There is a conflict for the FXMUX.  The design will
   exhibit suboptimal timing.
WARNING:Pack:266 - The function generator _n00731 failed to merge with F5
   multiplexer Ker10975.  There is a conflict for the FXMUX.  The design will
   exhibit suboptimal timing.
WARNING:DesignRules:367 - Netcheck: Loadless. Net N13705 has no load.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "GCLK_BUFGP" (output signal=GCLK_BUFGP)

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| GCLK                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| N<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<3>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<4>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<5>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<6>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| N<7>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| P<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| P<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| P<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| P<3>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| set1                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| set2                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.