📄 light.npl
字号:
JDF G
// Created by Project Navigator ver 1.0
PROJECT lighttest
DESIGN light
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s400
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE light.vhd
DEPASSOC light light.ucf
[Normal]
p_SimModelTarget=xstvlg, spartan3, Verilog.t_postMapSimModel, 1153013655, Modelsim_Verilog
xilxNgdbld_AUL=xstvlg, spartan3, Implementation.t_placeAndRouteDes, 1153013655, True
[STRATEGY-LIST]
Normal=True
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -