light.par

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

Constraints file: light.pcf

Loading device database for application Par from file "light_map.ncd".
   "light" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Resolved that IOB <N<0>> must be placed at site P96.
Resolved that IOB <N<1>> must be placed at site P95.
Resolved that IOB <N<2>> must be placed at site P94.
Resolved that IOB <N<3>> must be placed at site P93.
Resolved that IOB <N<4>> must be placed at site P85.
Resolved that IOB <N<5>> must be placed at site P76.
Resolved that IOB <N<6>> must be placed at site P62.
Resolved that IOB <N<7>> must be placed at site P61.
Resolved that IOB <P<0>> must be placed at site P102.
Resolved that IOB <P<1>> must be placed at site P101.
Resolved that IOB <P<2>> must be placed at site P100.
Resolved that IOB <P<3>> must be placed at site P97.
Resolved that IOB <GCLK> must be placed at site P79.
Resolved that IOB <set1> must be placed at site P64.
Resolved that IOB <set2> must be placed at site P65.


Device utilization summary:

   Number of External IOBs            15 out of 141    10%
      Number of LOCed External IOBs   15 out of 15    100%

   Number of SLICELs                 238 out of 3584    6%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal N13705 has no load

Phase 1.1
Phase 1.1 (Checksum:989c41) REAL time: 0 secs 

Phase 3.8
..................
Phase 3.8 (Checksum:99ed45) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file light.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1492 unrouted;       REAL time: 2 secs 

Phase 2: 1399 unrouted;       REAL time: 2 secs 

Phase 3: 438 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|        GCLK_BUFGP       |  BUFGMUX0| No   |   78 |  0.143     |  0.458      |
+-------------------------+----------+------+------+------------+-------------+
|            divclk       |   Local  |      |   34 |  1.616     |  2.640      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 153


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.874
   The MAXIMUM PIN DELAY IS:                               5.476
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.299

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1004         346          95          29          18           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  67 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file light.ncd.


PAR done.