light.twr

A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml light light.ncd -o
light.twr light.pcf


Design file:              light.ncd
Physical constraint file: light.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.26 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock GCLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
set1        |    4.965(R)|    0.511(R)|GCLK_BUFGP        |   0.000|
set2        |    4.793(R)|   -0.295(R)|GCLK_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock GCLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
N<0>        |   13.109(R)|GCLK_BUFGP        |   0.000|
N<1>        |   13.070(R)|GCLK_BUFGP        |   0.000|
N<2>        |   13.166(R)|GCLK_BUFGP        |   0.000|
N<3>        |   13.095(R)|GCLK_BUFGP        |   0.000|
N<4>        |   13.370(R)|GCLK_BUFGP        |   0.000|
N<5>        |   13.469(R)|GCLK_BUFGP        |   0.000|
N<6>        |   14.720(R)|GCLK_BUFGP        |   0.000|
N<7>        |   15.098(R)|GCLK_BUFGP        |   0.000|
P<0>        |   11.662(R)|GCLK_BUFGP        |   0.000|
P<1>        |   11.512(R)|GCLK_BUFGP        |   0.000|
P<2>        |   11.384(R)|GCLK_BUFGP        |   0.000|
P<3>        |   11.420(R)|GCLK_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock GCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
GCLK           |   11.761|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sun Jul 16 15:25:31 2006
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Peak Memory Usage: 59 MB