hdllib.ref

这是一个介绍32位RISC处理器软核的设计与验证

AR sent_receive_sch behavioral E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf sub00/vhpl05 1207730992
AR rcv_v behavioral E:/vhdl/myproject/sent_receive/rcv_v.vhd sub00/vhpl03 1207730990
AR fa_v behavioral E:/vhdl/myproject/sent_receive/fa_v.vhd sub00/vhpl01 1207738830
EN rcv_v NULL E:/vhdl/myproject/sent_receive/rcv_v.vhd sub00/vhpl02 1207730989
EN fa_v NULL E:/vhdl/myproject/sent_receive/fa_v.vhd sub00/vhpl00 1207738829
EN sent_receive_sch NULL E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf sub00/vhpl04 1207730991