testbench_arch.h

来自「这是一个介绍32位RISC处理器软核的设计与验证」· C头文件 代码 · 共 33 行

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Work_sent_receive_tbw_testbench_arch_H
#define H_Work_sent_receive_tbw_testbench_arch_H
#include "work/sent_receive_tbw/entity.h"
class Work_sent_receive_tbw_testbench_arch: public Work_sent_receive_tbw {
public:

HSim__s4 VV;
HSimAccessVar VY;
HSim__s4 C12;
HSim__s4 C16;
HSim__s4 C19;
    HSim__s1 SA[6];
    Work_sent_receive_tbw_testbench_arch(const char * name);
    ~Work_sent_receive_tbw_testbench_arch();
    void constructObject();
    virtual void archImplement(HSimConfigDecl* cfg);
};


#endif