entity.cpp

这是一个介绍32位RISC处理器软核的设计与验证

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "unisim.auxlib/vcomponents/vcomponents.h"
#include "ieee/numeric_std/numeric_std.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/sent_receive_sch/entity.h"

static const char *entFileName = "E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Work_sent_receive_sch::Work_sent_receive_sch(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"sent_receive_sch", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 10)

{
  SE[0].initialize("clk", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SE[1].initialize("input", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(4, 0, HSim::DOWNTO), this, HSim::PortSigIn, (const char*)0);
  ;
  SE[1].setDefaultValue((char *)0);
;
  SE[2].initialize("start", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SE[3].initialize("alm", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigOut);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SE[4].initialize("output", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(4, 0, HSim::DOWNTO), this, HSim::PortSigOut, (const char*)0);
  ;
  SE[4].setDefaultValue((char *)0);
;
  SE[5].initialize("re", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigOut);
  ;
  SE[5].setDefaultValue((char *)0);
;
  SetPorts();
 
}

Work_sent_receive_sch::~Work_sent_receive_sch()
{
}

void Work_sent_receive_sch::SetPorts()
{
}

void Work_sent_receive_sch::constructEntityObject()
{
;
}