hdpdeps.ref

这是一个介绍32位RISC处理器软核的设计与验证

V2 21
FL E:/vhdl/myproject/sent_receive/rcv_v.vhd 2008/04/09.16:26:58 H.38
EN work/RCV_V 1207731329           FL E:/vhdl/myproject/sent_receive/rcv_v.vhd \
      PB ieee/STD_LOGIC_1164 1106546471 PB ieee/STD_LOGIC_ARITH 1106546473 \
      PB ieee/STD_LOGIC_UNSIGNED 1106546479
AR work/RCV_V/BEHAVIORAL 1207731330 FL E:/vhdl/myproject/sent_receive/rcv_v.vhd \
      EN work/RCV_V 1207731329
FL E:/vhdl/myproject/sent_receive/sent_receive_tbw.vhw 2008/04/09.19:35:04 H.38
EN work/SENT_RECEIVE_TBW 1207740908 FL E:/vhdl/myproject/sent_receive/sent_receive_tbw.vhw \
      PH UNISIM/VCOMPONENTS 1106546621 PB ieee/STD_LOGIC_1164 1106546471 \
      PB ieee/NUMERIC_STD 1106546485 PB ieee/STD_LOGIC_TEXTIO 1106546481 \
      PB std/TEXTIO 1106546451
AR work/SENT_RECEIVE_TBW/TESTBENCH_ARCH 1207740909 \
      FL E:/vhdl/myproject/sent_receive/sent_receive_tbw.vhw \
      EN work/SENT_RECEIVE_TBW 1207740908 CP SENT_RECEIVE_SCH \
      PB ieee/STD_LOGIC_TEXTIO 1106546481
FL E:/vhdl/myproject/sent_receive/rcv_tbw.vhw 2008/04/09.19:32:22 H.38
EN work/RCV_TBW 1207740758         FL E:/vhdl/myproject/sent_receive/rcv_tbw.vhw \
      PB ieee/STD_LOGIC_1164 1106546471 PB ieee/STD_LOGIC_ARITH 1106546473 \
      PB ieee/STD_LOGIC_UNSIGNED 1106546479 PB ieee/STD_LOGIC_TEXTIO 1106546481 \
      PB std/TEXTIO 1106546451
AR work/RCV_TBW/TESTBENCH_ARCH 1207740759 FL E:/vhdl/myproject/sent_receive/rcv_tbw.vhw \
      EN work/RCV_TBW 1207740758 CP RCV_V  PB ieee/STD_LOGIC_TEXTIO 1106546481
FL E:/vhdl/myproject/sent_receive/fa_tbw.vhw 2008/04/09.19:01:10 H.38
EN work/FA_TBW 1207738875          FL E:/vhdl/myproject/sent_receive/fa_tbw.vhw \
      PB ieee/STD_LOGIC_1164 1106546471 PB ieee/STD_LOGIC_ARITH 1106546473 \
      PB ieee/STD_LOGIC_UNSIGNED 1106546479 PB ieee/STD_LOGIC_TEXTIO 1106546481 \
      PB std/TEXTIO 1106546451
AR work/FA_TBW/TESTBENCH_ARCH 1207738876 FL E:/vhdl/myproject/sent_receive/fa_tbw.vhw \
      EN work/FA_TBW 1207738875 CP FA_V    PB ieee/STD_LOGIC_TEXTIO 1106546481
FL E:/vhdl/myproject/sent_receive/fa_v.vhd 2008/04/09.19:00:22 H.38
EN work/FA_V 1207738873            FL E:/vhdl/myproject/sent_receive/fa_v.vhd \
      PB ieee/STD_LOGIC_1164 1106546471 PB ieee/STD_LOGIC_ARITH 1106546473 \
      PB ieee/STD_LOGIC_UNSIGNED 1106546479
AR work/FA_V/BEHAVIORAL 1207738874 FL E:/vhdl/myproject/sent_receive/fa_v.vhd EN work/FA_V 1207738873
FL E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf 2008/04/09.19:34:24 H.38
EN work/SENT_RECEIVE_SCH 1207740906 FL E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf \
      PB ieee/STD_LOGIC_1164 1106546471 PB ieee/NUMERIC_STD 1106546485 \
      PH UNISIM/VCOMPONENTS 1106546621
AR work/SENT_RECEIVE_SCH/BEHAVIORAL 1207740907 \
      FL E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf \
      EN work/SENT_RECEIVE_SCH 1207740906 CP FA_V CP RCV_V